Quartus怎么根据VHDL程序生成元件? 100
根据以下程序如何才能生成封装的元件,还可以再调用的。libraryieee;useieee.std_logic_arith.all;useieee.std_logic_1...
根据以下程序如何才能生成封装的元件,还可以再调用的。
library ieee;
use ieee.std_logic_arith.all;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity modulation is
port(clk :in std_logic;
start :in std_logic;
basedatain :in std_logic;
qpskout :out std_logic;
clk2 :out std_logic);
end modulation;
architecture behav of modulation is
signal q:integer range 0 to 7;
signal xx:std_logic_vector(1 downto 0);
signal yy:std_logic_vector(1 downto 0);
signal f:std_logic_vector(3 downto 0);
begin
process(clk)
begin
if clk'event and clk='1' then
if start='0' then q<=0;
elsif q=0 then q<=1;f(3)<='1'; f(1)<='0';xx(1)<=basedatain;yy<=xx;
elsif q=2 then q<=3;f(2)<='0'; f(0)<='1';
elsif q=4 then q<=5;f(3)<='0'; f(1)<='1'; xx(0)<=basedatain;
elsif q=6 then q<=7;f(2)<='1'; f(0)<='0';
else q<=q+1;
end if;
end if;
end process;
clk2<=NOT clk;
qpskout<=f(0) when yy="11" else
f(1) when yy="10" else
f(2) when yy="01" else
f(3);
end behav;
要是哪位大侠会的话能教教我吗? 展开
library ieee;
use ieee.std_logic_arith.all;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity modulation is
port(clk :in std_logic;
start :in std_logic;
basedatain :in std_logic;
qpskout :out std_logic;
clk2 :out std_logic);
end modulation;
architecture behav of modulation is
signal q:integer range 0 to 7;
signal xx:std_logic_vector(1 downto 0);
signal yy:std_logic_vector(1 downto 0);
signal f:std_logic_vector(3 downto 0);
begin
process(clk)
begin
if clk'event and clk='1' then
if start='0' then q<=0;
elsif q=0 then q<=1;f(3)<='1'; f(1)<='0';xx(1)<=basedatain;yy<=xx;
elsif q=2 then q<=3;f(2)<='0'; f(0)<='1';
elsif q=4 then q<=5;f(3)<='0'; f(1)<='1'; xx(0)<=basedatain;
elsif q=6 then q<=7;f(2)<='1'; f(0)<='0';
else q<=q+1;
end if;
end if;
end process;
clk2<=NOT clk;
qpskout<=f(0) when yy="11" else
f(1) when yy="10" else
f(2) when yy="01" else
f(3);
end behav;
要是哪位大侠会的话能教教我吗? 展开
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