Question

fpga 简单编解码器的设计，我用VHDL，Quartus，拜托各位大侠了

Answer 1

LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY encoder IS
PORT(input : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
y : OUT STD_LOGIC_VECTOR(2 DOWNTO 0));
END encoder;
ARCHITECTURE rtl OF encoder IS
BEGIN
PROCESS(input)
BEGIN
CASE input IS
WHEN “01111111”=>y<=“111”;
WHEN “10111111”=>y<=“110”;
WHEN “11011111”=>y<=“101”;
WHEN “11101111”=>y<=“100”;
WHEN “11110111”=>y<=“011”;
WHEN “11111011”=>y<=“010”;
WHEN “11111101”=>y<=“001”;
WHEN “11111110”=>y<=“000”;
WHEN OTHERS=>y<=“XXX”;
END CASE;
END PROCESS;
END rtl;

Answer 2

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