Question

六十进制计数器用VHDL语言 写的对不？哪错了，求指点

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY counter_60 IS
PORT(clk: IN STD_LOGIC;
b1,b2,q: OUT STD_LOGIC;
q: OUT INTEGER RANGE 59 downto 0;);
END counter_60;
ARCHITECTURE a OF counter_60 IS
SIGNAL temp1:INTEGER RANGE 9 downto 0;
SIGNAL temp2:INTEGER RANGE 5 downto 0;
BEGIN
PROCESS(clk)
BEGIN
IF clk'event AND clk='1' THEN
IF temp1=9 THEN
temp1<="0000";
b1<='1';
IF temp2=5 THEN
temp2="0000";
b2<='1';
ELSE
temp2<=temp2+1;
b2<='0';
ELSE
temp1<=temp1+1;
b1<='0';
END IF;
q<=temp2&temp1;
END IF;
END IF;
END PROCESS;
END a;

Answer 1

q定义的有问题。层次有点乱。判断59后再做个位，十位处理就简单化了