Question

VHDL中使用case_when语句出现语法错误

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;use
IEEE.STD_LOGIC_UNSIGNED.ALL;
entity process4 is
Port ( qout : in STD_LOGIC_vector(3 downto 0);
seg_dis : out STD_LOGIC_vector(6 downto 0));
end process4;
architecture Behavioral of process4 is
process(qout)
begin
case qout is
when"0000" => seg_dis <= "1000000";
when"0001" => seg_dis <= "1111001";
when"0010" => seg_dis <= "0100100";
when"0011" => seg_dis <= "0110000";
when"0100" => seg_dis <= "0011001";
when"0101" => seg_dis <= "0010010";
when"0110" => seg_dis <= "0000010";
when"0111" => seg_dis <= "1111000";
when"1000" => seg_dis <= "0000000";
when"1001" => seg_dis <= "0010000";
when"1010" => seg_dis <= "0001000";
when"1011" => seg_dis <= "0000011";
when"1100" => seg_dis <= "1000110";
when"1101" => seg_dis <= "0100001";
when"1110" => seg_dis <= "0000110";
when"1111" => seg_dis <= "0001110";
when others => seg_dis <= "1111111";
end case;
end process;
end Behavioral;

这里出现了Error (10500): VHDL syntax error at process4.vhd(28) near text "when"; expecting "end", or "(", or an identifier ("when" is a reserved keyword), or a concurrent statement这样的报错信息，请问怎么解决？

Answer 1

process(qout) 前面一行少一个begin

追问

map(SETn=>'1',CLRn=>sclr,J=>'1',K=>'1',CLK=>cp1,q=>sq,nq=>nq1);
能请教一下map中给信号赋值的语句吗？譬如SETn=>'1'该怎么理解，是将该信号赋值为1吗？

追答

是的，就是赋值为1的意思。