Question

quartus ii 程序问题 初学VHDL 求大神指点

初学VHDL 求指点
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity jishu1 is
port(fin,start,reset:in std_logic;
km:out std_logic);
end jishu1;
architecture one of jishu1 is
begin
process(fin,start,reset)
variable cnt:integer;
begin
if start='0' then km<='0';
elsif reset='1' then km<='0';
elsif fin'event and fin='1' then
cnt:=cnt+1;km<='0';
if cnt=10 then
km<='1';cnt:=0;
end if;
end if;
end process;
end one;
编译没问题

我想问下为什么没有计数呢？

Answer 1

cnt:=cnt+1;km<='0';
if cnt=10 then
km<='1';cnt:=0;
end if;
改成
cnt:=cnt+1;
if cnt=10 then
km<='1';cnt:=0;
else km<='0';
end if;
试一试

追问

没用

追答

试试这个吧：
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity jishu1 is
port(fin,start,reset:in std_logic;
km:out std_logic);
end jishu1;
architecture one of jishu1 is
signal cnt:integer;
begin
process(fin,start,reset)
begin
if start='0' then km<='0'; cnt<=0;
elsif reset='1' then km<='0';cnt<=0;
elsif fin'event and fin='1' then
cnt<=cnt+1;
if cnt=10 then
km<='1';cnt<=0;
else km<='0';
end if;
end if;
end process;
end one;