EDA的高手帮忙看下这个程序VHDL语言写的,不知道哪错了, 40
程序源码:一个简单的3——8译码器:LIBRARYIEEE;USEIEEE.STD_LOGIC_1164.ALL;USEIEEE.STD_LOGIC_UNSIGNED.A...
程序源码:一个简单的3——8译码器:
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY ymq IS
PORT(a,b,c : IN STD_LOGIC;
y0,y1,y2,y3,y4,y5,y6,y7 : OUT STD_LOGIC);
END ymq;
ARCHITECTURE bd OF ymq IS
SIGNAL y:STD_LOGIC_VECTOR(7 DOWNTO 0);
SIGNAL q:STD_LOGIC_VECTOR(2 DOWNTO 0);
BEGIN
q<=a&b&c;
y<=y7&y6&y5&y4&y3&y2&y1&y0;
PROCESS(q)
BEGIN
y<="11111110" WHEN q="000" ELSE
"11111101" WHEN q="001" ELSE
"11111011" WHEN q="010" ELSE
"11110111" WHEN q="011" ELSE
"11101111" WHEN q="100" ELSE
"11011111" WHEN q="101" ELSE
"10111111" WHEN q="110" ELSE
"01111111" WHEN q="111" ELSE
"11111111";
END PROCESS;
END bd; 展开
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY ymq IS
PORT(a,b,c : IN STD_LOGIC;
y0,y1,y2,y3,y4,y5,y6,y7 : OUT STD_LOGIC);
END ymq;
ARCHITECTURE bd OF ymq IS
SIGNAL y:STD_LOGIC_VECTOR(7 DOWNTO 0);
SIGNAL q:STD_LOGIC_VECTOR(2 DOWNTO 0);
BEGIN
q<=a&b&c;
y<=y7&y6&y5&y4&y3&y2&y1&y0;
PROCESS(q)
BEGIN
y<="11111110" WHEN q="000" ELSE
"11111101" WHEN q="001" ELSE
"11111011" WHEN q="010" ELSE
"11110111" WHEN q="011" ELSE
"11101111" WHEN q="100" ELSE
"11011111" WHEN q="101" ELSE
"10111111" WHEN q="110" ELSE
"01111111" WHEN q="111" ELSE
"11111111";
END PROCESS;
END bd; 展开
2个回答
展开全部
再来一个信号...不能对输出的作为输入。。或者改为inout。。。buffer之类的。。最好在用信号。。
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