Question

quartus ii9.0verilog 程序问题

在QuartusII环境下编译一个很简单的程序，只有警告，没有错误。警告如下 Warning: Timing characteristics of device EP2C5Q208C8 are preliminaryWarning: Found 4 output pins without output pin load capacitance assignmentWarning: Found 4 output pins without output pin load capacitance assignment Warning: Pin "q[0]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis Warning: Pin "q[1]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis Warning: Pin "q[2]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis Warning: Pin "q[3]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis Warning: Found pins functioning as undefined clocks and/or memory enablesInfo: Assuming node "clk" is an undefined clock这种警告能彻底解决吗，有什么影响 啊？哪位大侠指导一下迷途小书生。感激不尽。

Answer 1

为什么不把程序写出来更容易解决？
Found 4 output pins without output pin load capacitance assignment

这个问题对程序没有影响，你可以把这个警告隐藏起来，下次遇到同样的不就看不到了？
Warning: Found pins functioning as undefined clocks and/or memory enables
Info: Assuming node "clk" is an undefined clock
这里说的是你的程序没有定义时钟，那你写的程序应该是组合逻辑电路。
其他的也没有大影响