Question

verilog HDL中这句话是什么意思

wire pll_rst;
reg rst_r1,rst_r2;
always @(posedge clk or negedge rst_n)
if(!rst_n) rst_r1 <= 1'b1;
else rst_r1 <= 1'b0;
always @(posedge clk or negedge rst_n)
if(!rst_n) rst_r2 <= 1'b1;
else rst_r2 <= rst_r1;
assign pll_rst = rst_r2;

Answer 1

复位信号的“异步复位，同步释放”。
但是代码应该改一下。这里复位信号是低有效，rst_n是芯片pin脚上的复位信号。

wire pll_rst;
reg rst_r1,rst_r2;
always @(posedge clk or negedge rst_n)
if(!rst_n) rst_r1 <= 1'b0;
else rst_r1 <= 1'b1;
always @(posedge clk or negedge rst_n)
if(!rst_n) rst_r2 <= 1'b0;
else rst_r2 <= rst_r1;
assign pll_rst = rst_r2;