Question

这里有一段VHDL语言，有一个错误，怎么改正

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity yimaqi is
port(a,b,c,d,e,f,g:in std_logic;
selt :out std_logic_vector(2 downto 0)
);
end yimaqi;

architecture guo of yimaqi is
signal sel:std_logic_vector(6 downto 0);
begin
selt<=a&b&c&d&e&f&g;
process(sel)
begin
case selt is
when "0111111"=>selt<="110";
when "1011111"=>selt<="110";
when "1101111"=>selt<="110";
when "1110111"=>selt<="110";
when "1111011"=>selt<="110";
when "1111101"=>selt<="110";
when "1111110"=>selt<="110";
when "1111111"=>selt<="111";
when others =>selt<="000";
end case;
end process;
end guo;
Error (10309): VHDL Interface Declaration error in yimaqi.vhd(17): interface object "selt" of mode out cannot be read. Change object mode to buffer.

Answer 1

library ieee;
use ieee.std_logic_1164.all;

entity yimaqi is
port(a,b,c,d,e,f,g:in std_logic;
selt :out std_logic_vector(2 downto 0));
end yimaqi;

architecture guo of yimaqi is
signal sel:std_logic_vector(6 downto 0);
begin
sel <=a&b&c&d&e&f&g;
process(sel)
begin
case sel is
when "0111111"|"1011111"|"1101111"|"1110111"|"1111011"|"1111101"|"1111110"=>selt<="110";
when "1111111"=>selt<="111";
when others =>selt<="000";
end case;
end process;
end guo;

Answer 2

process(selt) 你写成了sel

追问

这样改之后就有两个错误了Error (10309): VHDL Interface Declaration error in yimaqi.vhd(17): interface object "selt" of mode out cannot be read.

追答

端口那里 定义了 selt是三位的，结构体里面又把selt并置成了7位？ ？？
signal sel:std_logic_vector(6 downto 0);
begin
sel<=a&b&c&d&e&f&g;
process(sel)
begin
case sel is

你自己把sel跟selt混淆的一塌糊涂了。 所以，你不应该用这样的信号跟端口很相似的名称。刚开始，我也没看清楚只是觉得别扭