VHDL；完成一个0~9之间循环计数的计数器,能在时钟信号的上升沿和下降沿都实现计数值的加1动作.求大神帮忙
LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
USE IEEE.std_logic_unsigned.ALL;
ENTITY double_counter IS
PORT(clk:IN std_logic;
counter_out:OUT std_logic_vector(3 DOWNTO 0));
END double_counter;
ARCHITECTURE bhv OF double_counter IS
SIGNAL counter:std_logic_vector(3 DOWNTO 0):=(OTHERS => '0');
SIGNAL adder,rising_counter,falling_counter:std_logic_vector(3 downto 0);
BEGIN
PROCESS(counter)
BEGIN
IF counter="1001" THEN adder <= (OTHERS => '0');
ELSE adder <= counter + 1;
END IF;
END PROCESS;
PROCESS(clk)
BEGIN
IF rising_edge(clk) THEN
rising_counter <= adder;
END IF;
END PROCESS;
PROCESS(clk)
BEGIN
IF falling_edge(clk) THEN
falling_counter <= adder;
END IF;
END PROCESS;
PROCESS(clk,rising_counter,falling_counter)
BEGIN
IF clk='0' THEN
counter <= rising_counter;
ELSE
counter <= falling_counter;
END IF;
END PROCESS;
counter_out <= counter;
END;
