Question

三人表决器怎样用vhdl编写

利用eda技术实现的y=ab+ac+bc

Answer 1

library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;entity XXX is
port (
A : in std_logic ;
B : in std_logic ;
C : in std_logic ;
Y : out std_logic
);
end XXX;architecture YYY of XXX isbegin
Y <= A and B or A and C or B and C ;
end YYY;