Question

求大神指点，下面这个FPGA程序的问题是什么，怎么修改？

Answer 1

不知能不能帮到你，
下面是vhdl中procedure的语法：
http://www.ics.uci.edu/~jmoorkan/vhdlref/procedur.html

A procedure may declare local variables. These do not retain their values between successive calls, but are re-initialised each time. Array-type parameters may be unconstrainedprocedure PARITY
(signal X : in std_ulogic_vector;
signal Y : out std_ulogic) is
variable TMP : std_ulogic := '0';
begin
for J in X'range loop
TMP := TMP xor X(J);
end loop; -- works for any size X
Y <= TMP;
end PARITY;

procedure中只能定义variable,不能定义signal.