Question

关于verilog测试激励问题！求大神帮忙！

自己写了一个程序如下：
`timescale 1ns/100ps
module bank_men(
clk, write_en,
data_in,
data_out);
input clk;
input write_en;
input [7:0] data_in;
output [7:0] data_out;
reg[7:0]bank;
always @ (posedge clk)
if (write_en)
#10 bank=data_in;
else
#10 bank=8'b0;
assign #20 data_out = bank;
endmodule
测试激励为：
`timescale 1ns/100ps
module testbench;
reg [7:0] data_in;
reg write_en=1;
reg clk=1;
wire [7:0]data_out=8'b0;
bank_men U1(
.clk(clk),
.write_en(write_en),
.data_in(data_in),
.data_out(data_out));
always
begin
#10 data_in=8'b11110010;
end
endmodule
用modesim仿真，输出没有波形。哪里出问题了！求大神帮忙.

Answer 1

always @ (posedge clk)
表示上升沿触发
测试激励中的clk一直为高电平，当然没输出了