Question

Error （10170）：Verilog HDL syntax error at add

module add(clk,start,stop,sum,count_out);
input clk,start,stop;
output [3:0] sum;
output count_out;
reg [3:0] sum;
reg count_out;

always @(posedge clk)
if(stop)
sum=4'b0000;
else
if(start)
begin
if(sum>=4'b1001)
sum<=4'b0000;
count_out<=1;
else if
sum<=sum+1'b1;
count_out<=0;
end
else sum<=sum;
endmodule

Error （10170）：Verilog HDL syntax error at add.v(17) near text "else"';expecting "end"
Error （10112）:Ignored design unit "add" at add.v(1) due to previous errors

急求解决办法啊，设计的是一个10进制加法器，count_out是进位信号。谢谢好心人了！

Answer 1

begin ... end缺失吧？

module add(clk,start,stop,sum,count_out);
input clk,start,stop;
output [3:0] sum;
output count_out;
reg [3:0] sum;
reg count_out;

always @(posedge clk)
if(stop)
sum=4'b0000; // 此处只有一个语句，可加可不加begin ... end。
else if(start) //
begin
if(sum>=4'b1001)
begin
sum<=4'b0000;
count_out<=1;
end
else // 此处没有条件 就不要用else if
begin
sum<=sum+1'b1;
count_out<=0;
end
end
else sum<=sum;
endmodule

Answer 2

count_out<=1;在这个语句后面加一个end；就是你程序的第17行，前面有begin后面不加end，这么简单的错误要注意啊！！还有你的程序名称add是不能用的，改一个名字。