Question

用Modelsim仿真VHDL程序，提示错误如下，请大神帮忙看一下是怎么回事，在线等。。。

** Error: C:/Users/spectre/Desktop/mod/DDS.v(1): near ";": syntax error, unexpected ';', expecting "STRING_LITERAL"
相应的程序段是：
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity DDS is
generic(ACCWidth : Integer := 16);
port (
CLK: in std_logic;
STEP: in std_logic_vector(ACCWidth-1 downto 0);
CHOICE: in std_logic_vector(1 downto 0);
Key : in std_logic;
DAOUT : out std_logic_vector(7 downto 0)
);
end;
architecture DDS of DDS is
signal ACC:std_logic_vector(ACCWidth-1 downto 0):=(others =>'0');
signal KEYADD:std_logic_vector(ACCWidth-1 downto 0):="0000000011111111";
begin
process(CLK) --,STEP
begin
if(CLK'event and CLK='1') then
ACC <=ACC+KEYADD;
end if;
end process;
process(key)
begin
if(key'event and key='1') then
KEYADD<=KEYADD+1;
end if;
end process;
第一行还有这个。。。忘打上去了
library ieee;

Answer 1

楼主用的tcl语句编译吗 还是工具栏选择complie 选中该.vhd文件？
如果是前者，请用vcom编译.vhd；vlog 编译.v

Answer 2

实体名干麻要和结构名称一样

追问

貌似问题不是出在这里吧，这个程序在Quartus II上编译是通过的，换在Modelsim上进行仿真的话就有这个问题了