Question

用Verilog HDL语言设计一个具有复位和计数功能的4位计数器.

Answer 1

我写的一个十进制计数，可以复位，置数，使能，双向计数，请参考
`timescale 1ns/100ps
module count(
clk,
nrst,
ncs,
s,
load,
load_data,
q
);

input clk;
input nrst;
input ncs;
input s;
input load;
input [3:0] load_data;
output [3:0] q;
reg [3:0] q;

always @(posedge clk or negedge nrst) begin
if(!nrst) begin
q<=4'b0000;
end else if(!ncs) begin
q<=4'b0000;
end else if(load==1'b1) begin
q<=load_data;
end else if(s==1'b1) begin
if(q==4'b1001) begin
q<=4'b0000;
end else begin
q<=q+4'b0001;
end
end else if(s==1'b0) begin
if(q==4'b0000) begin
q<=4'b1001;
end else begin
q<=q-4'b0001;
end
end
end
endmodule