Question

设计含有异步清零和计数使能的16位二进制减法计数器。

VHDL

Answer 1

解： 设clr为异步清零端，en为计数使能端
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
ENTITY ex6_9 IS
port(
clk : IN STD_LOGIC;
clr,en : in std_logic;
cnt : OUT std_logic_vector(15 downto 0)
);
END ;
ARCHITECTURE hdlarch OF ex6_9 IS
signal cnttmp : std_logic_vector(15 downto 0);
BEGIN
process(clk,clr) begin
if clr = '1' then
cnttmp <= (others => '0');
elsif(rising_edge(clk)) then
if en = '1' then
cnttmp <= cnttmp + 1;
end if;
end if;
end process;
cnt <= cnttmp;
END;

Answer 2

http://jpkc.hdu.edu.cn/elec/eda/sor/%CF%B0%CC%E2%BD%E2%B4%F0.pdf你把这个下载下来看看