Question

fpga串口通信程序纠错，编译通过，下载后TXD灯常亮，数码管显示00

以下是接收模块
module usart_rx
(
clk,rst_n,clk_bps,start_rx,rs232_in,bps_start,rx_data,rx_finish
);
input clk;
input clk_bps;
input rst_n;
input start_rx;
input rs232_in;
output bps_start;
output[7:0]rx_data;
output rx_finish;
reg[3:0]count;
reg bps_start_r;
reg rx_finish;
reg[7:0]rx_data_r;
always@(posedge clk or negedge rst_n)
if(!rst_n)
begin
count<=4'd0;
bps_start_r<=1'b0;
rx_finish<=1'b0;
rx_data_r<=8'd0;
end
else
case(count)
4'd0:if(start_rx)begin bps_start_r<=1'b1;count<=count+1'b1;end
4'd1:if(clk_bps)begin count<=count+1'b1;end
4'd2:if(clk_bps)begin rx_data_r[0]<=rs232_in;count<=count+1'b1;end
4'd3:if(clk_bps)begin rx_data_r[1]<=rs232_in;count<=count+1'b1;end
4'd4:if(clk_bps)begin rx_data_r[2]<=rs232_in;count<=count+1'b1;end
4'd5:if(clk_bps)begin rx_data_r[3]<=rs232_in;count<=count+1'b1;end
4'd6:if(clk_bps)begin rx_data_r[4]<=rs232_in;count<=count+1'b1;end
4'd7:if(clk_bps)begin rx_data_r[5]<=rs232_in;count<=count+1'b1;end
4'd8:if(clk_bps)begin rx_data_r[6]<=rs232_in;count<=count+1'b1;end
4'd9:if(clk_bps)begin rx_data_r[7]<=rs232_in;count<=count+1'b1;end
4'd10:if(clk_bps)count<=count+1'b1;
4'd11:if(clk_bps)count<=count+1'b1;
4'd12:begin bps_start_r<=1'b0;count<=count+1'b1;end
4'd13:begin rx_finish<=1'b1;count<=1'd0;end
default:;
endcase
assign bps_start=bps_start_r;

assign rx_data=rx_data_r;
endmodule
以下是发送模块
module usart_tx
(
clk,rst_n,clk_bps,rx_data,rx_finish,rs232_out,bps_start
);
input clk;
input rst_n;
input rx_finish;
input clk_bps;
input[7:0] rx_data;
output rs232_out;
output bps_start;
reg[7:0]tx_data;
reg[3:0]count1;
reg bps_start_r;
reg start_tx;
reg rs232_out_r;
always@(posedge clk or negedge rst_n)
if(!rst_n)
begin
count1<=4'd0;
start_tx<=1'b0;
bps_start_r<=1'b0;
tx_data<=8'd0;
end
else if(rx_finish)
begin
start_tx<=1'b1;
bps_start_r<=1'b1;
tx_data<=rx_data;
end
else
case(count1)
4'd0:if(clk_bps)begin rs232_out_r<=1'b0;count1<=count1+1'b1;end
4'd1:if(clk_bps)begin rs232_out_r<=tx_data[0];count1<=count1+1'b1;end
4'd2:if(clk_bps)begin rs232_out_r<=tx_data[1];count1<=count1+1'b1;end
4'd3:if(clk_bps)begin rs232_out_r<=tx_data[2];count1<=count1+1'b1;end
4'd4:if(clk_bps)begin rs232_out_r<=tx_data[3];count1<=count1+1'b1;end
4'd5:if(clk_bps)begin rs232_out_r<=tx_data[4];count1<=count1+1'b1;end
4'd6:if(clk_bps)begin rs232_out_r<=tx_data[5];count1<=count1+1'b1;end
4'd7:if(clk_bps)begin rs232_out_r<=tx_data[6];count1<=count1+1'b1;end
4'd8:if(clk_bps)begin rs232_out_r<=tx_data[7];count1<=count1+1'b1;end
4'd9:if(clk_bps)begin rs232_out_r<=1'b1;count1<=count1+1'b1;end
4'd10:if(clk_bps)begin rs232_out_r<=1'b1;count1<=count1+1'b1;end
4'd11:begin bps_start_r<=1'b0;count1<=count1+1'b1;end
4'd12:begin start_tx<=1'b0;count1<=1'd0;end
default:;
endcase
assign bps_start=bps_start_r;
assign rs232_out=rs232_out_r;
endmodule

Answer 1

你的本意是收发握手无限循环吗？
rx_finish在第一次接收完成后就常'1'了，所以tx端从第二次发送开始就变成连续发送了。
假定收发数据本身都是正确的，发送的数据"rx_data"就是从rx模块连过来的，那么数据一直是0就对了，因为初始化就是发送0，中间不论循环收发多少次，都是直接转发，所以常0很正常。

另外问一下：
你的clk、clk_bps是几倍频率差距？
一个周期clk_bps的波形是宽度为一个clk周期的脉冲还是占空比50:50？
问这个的意思是clk_bps过宽的话你的状态机会因此而"打滑"~~