求用FPGA编写的VHDL流水灯程序,非常感谢,要求:有一个开关控制流水方向,200ms变化一次
2个回答
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY seg70 IS
PORT (
clk : IN std_logic; --clk 50MHZ
rst : IN std_logic; --REST
dataout : OUT std_logic_vector(7 DOWNTO 0); --各段数据输出
en : OUT std_logic_vector(7 DOWNTO 0)); --COM使能输出
END seg70;
ARCHITECTURE arch OF seg70 IS
signal cnt_scan : std_logic_vector(25 downto 0 );--计数器分频用
signal data4 : std_logic_vector(2 downto 0);
signal dataout_xhdl1 : std_logic_vector(7 downto 0);
signal en_xhdl : std_logic_vector(7 downto 0);
begin
dataout<=dataout_xhdl1;
en<=en_xhdl;
process(clk,rst)
begin
if(rst='0')then
cnt_scan<="00000000000000000000000000";
elsif(clk'event and clk='1')then
cnt_scan<=cnt_scan+1; --计数器累加
end if;
end process;
process(cnt_scan(25 downto 23)) --计数器分频
begin
case cnt_scan(25 downto 23) is --这里有8种状态,一个状态的时间间隔是一样的。
when"000"=> en_xhdl<="11111110"; --每一次轮流选择一排点阵灯
when"001"=> en_xhdl<="11111101";
when"010"=> en_xhdl<="11111011";
when"011"=> en_xhdl<="11110111";
when"100"=> en_xhdl<="11101111";
when"101"=> en_xhdl<="11011111";
when"110"=> en_xhdl<="10111111";
when"111"=> en_xhdl<="01111111";
when others=> en_xhdl<="11111111";
end case;
end process;
process(en_xhdl)
begin
case en_xhdl is
--每一选择一排灯,同时还要给点阵的数据端口送数据
when "11111110"=> data4<="000";
when "11111101"=> data4<="001";
when "11111011"=> data4<="010";
when "11110111"=> data4<="011";
when "11101111"=> data4<="100";
when "11011111"=> data4<="101";
when "10111111"=> data4<="110";
when "01111111"=> data4<="111";
when others => data4<="000";
end case;
end process;
process(data4)
begin
case data4 is
WHEN "000" => --给点阵的数据端口送数据 每一次都是8个点亮。都是0
dataout_xhdl1 <= "00000000";
WHEN "001" =>
dataout_xhdl1 <= "00000000";
WHEN "010" =>
dataout_xhdl1 <= "00000000";
WHEN "011" =>
dataout_xhdl1 <= "00000000";
WHEN "100" =>
dataout_xhdl1 <= "00000000";
WHEN "101" =>
dataout_xhdl1 <= "00000000";
WHEN "110" =>
dataout_xhdl1 <= "00000000";
WHEN "111" =>
dataout_xhdl1 <= "00000000";
WHEN OTHERS =>
dataout_xhdl1 <= "00000000";
END CASE;
END PROCESS;
end arch;
不是你所要求的,以前自己写的,仅供参考
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY seg70 IS
PORT (
clk : IN std_logic; --clk 50MHZ
rst : IN std_logic; --REST
dataout : OUT std_logic_vector(7 DOWNTO 0); --各段数据输出
en : OUT std_logic_vector(7 DOWNTO 0)); --COM使能输出
END seg70;
ARCHITECTURE arch OF seg70 IS
signal cnt_scan : std_logic_vector(25 downto 0 );--计数器分频用
signal data4 : std_logic_vector(2 downto 0);
signal dataout_xhdl1 : std_logic_vector(7 downto 0);
signal en_xhdl : std_logic_vector(7 downto 0);
begin
dataout<=dataout_xhdl1;
en<=en_xhdl;
process(clk,rst)
begin
if(rst='0')then
cnt_scan<="00000000000000000000000000";
elsif(clk'event and clk='1')then
cnt_scan<=cnt_scan+1; --计数器累加
end if;
end process;
process(cnt_scan(25 downto 23)) --计数器分频
begin
case cnt_scan(25 downto 23) is --这里有8种状态,一个状态的时间间隔是一样的。
when"000"=> en_xhdl<="11111110"; --每一次轮流选择一排点阵灯
when"001"=> en_xhdl<="11111101";
when"010"=> en_xhdl<="11111011";
when"011"=> en_xhdl<="11110111";
when"100"=> en_xhdl<="11101111";
when"101"=> en_xhdl<="11011111";
when"110"=> en_xhdl<="10111111";
when"111"=> en_xhdl<="01111111";
when others=> en_xhdl<="11111111";
end case;
end process;
process(en_xhdl)
begin
case en_xhdl is
--每一选择一排灯,同时还要给点阵的数据端口送数据
when "11111110"=> data4<="000";
when "11111101"=> data4<="001";
when "11111011"=> data4<="010";
when "11110111"=> data4<="011";
when "11101111"=> data4<="100";
when "11011111"=> data4<="101";
when "10111111"=> data4<="110";
when "01111111"=> data4<="111";
when others => data4<="000";
end case;
end process;
process(data4)
begin
case data4 is
WHEN "000" => --给点阵的数据端口送数据 每一次都是8个点亮。都是0
dataout_xhdl1 <= "00000000";
WHEN "001" =>
dataout_xhdl1 <= "00000000";
WHEN "010" =>
dataout_xhdl1 <= "00000000";
WHEN "011" =>
dataout_xhdl1 <= "00000000";
WHEN "100" =>
dataout_xhdl1 <= "00000000";
WHEN "101" =>
dataout_xhdl1 <= "00000000";
WHEN "110" =>
dataout_xhdl1 <= "00000000";
WHEN "111" =>
dataout_xhdl1 <= "00000000";
WHEN OTHERS =>
dataout_xhdl1 <= "00000000";
END CASE;
END PROCESS;
end arch;
不是你所要求的,以前自己写的,仅供参考
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