Question

vhdl语句问题

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY MULTI IS
PORT(A,B:IN STD_LOGIC_VECTOR(3 DOWNTO 0);
Y:OUT STD_LOGIC_VECTOR(7 DOWNTO 0));
END ENTITY MULTI;
ARCHITECTURE ART OF MULTI IS
SIGNAL M,N,P,Q:STD_LOGIC_VECTOR(7 DOWNTO 0);
BEGIN
L1:BLOCK
BEGIN
PROCESS(A,B) IS
BEGIN
IF A(0)='1' THEN
M(3 DOWNTO 0)<=B(3 DOWNTO 0);
M(7 DOWNTO 4)<="0000";
ELSE
M(7 DOWNTO 0)<="00000000";
END IF;
IF A(1)='1' THEN
N(4 DOWNTO 1)<=B(3 DOWNTO 0);
N(0)<='0';
N(7 DOWNTO 5)<="000";
ELSE
N(7 DOWNTO 0)<="00000000";
END IF;
IF A(2)='1' THEN
P(5 DOWNTO 2)<=B(3 DOWNTO 0);
P(1 DOWNTO 0)<="00";
P(7 DOWNTO 6)<="00";
ELSE
P(7 DOWNTO 0)<="00000000";
END IF;
IF A(3)='1' THEN
Q(6 DOWNTO 3)<=B(3 DOWNTO 0);
Q(2 DOWNTO 0)<="000";
Q(7)<='0';
ELSE
Q(7 DOWNTO 0)<="00000000";
END IF;
END PROCESS;
END BLOCK L1;
PROCESS(M,N,P,Q) IS
BEGIN
Y<=M+N+P+Q;
END PROCESS;
END ARCHITECTURE ART;

这段代码是什么意思？每句话的意思分别是什么

Answer 1

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;

ENTITY MULTI IS --定义实体MULTI
PORT(A,B:IN STD_LOGIC_VECTOR(3 DOWNTO 0);--两个输入A、B，一个输出Y
Y:OUT STD_LOGIC_VECTOR(7 DOWNTO 0));
END ENTITY MULTI;

ARCHITECTURE ART OF MULTI IS--结构体
SIGNAL M,N,P,Q:STD_LOGIC_VECTOR(7 DOWNTO 0);--定义信号M、N、P、Q
BEGIN
L1:BLOCK--定义程序块L1
BEGIN
PROCESS(A,B) IS--过程
BEGIN
IF A(0)='1' THEN--如果A0=1，则给M赋值0000&B[0..3],否则为00000000；
M(3 DOWNTO 0)<=B(3 DOWNTO 0);
M(7 DOWNTO 4)<="0000";
ELSE
M(7 DOWNTO 0)<="00000000";
END IF;
IF A(1)='1' THEN--如果A1=1，则给N赋值000&B[0..3]&0,否则为00000000；
N(4 DOWNTO 1)<=B(3 DOWNTO 0);
N(0)<='0';
N(7 DOWNTO 5)<="000";
ELSE
N(7 DOWNTO 0)<="00000000";
END IF;
IF A(2)='1' THEN--如果A2=1，则给P赋值00&B[0..3]&00,否则为00000000；
P(5 DOWNTO 2)<=B(3 DOWNTO 0);
P(1 DOWNTO 0)<="00";
P(7 DOWNTO 6)<="00";
ELSE
P(7 DOWNTO 0)<="00000000";
END IF;
IF A(3)='1' THEN--如果A3=1，则给Q赋值0&B[0..3]&000,否则为00000000；
Q(6 DOWNTO 3)<=B(3 DOWNTO 0);
Q(2 DOWNTO 0)<="000";
Q(7)<='0';
ELSE
Q(7 DOWNTO 0)<="00000000";
END IF;
END PROCESS;
END BLOCK L1;

PROCESS(M,N,P,Q) IS--过程，一旦M、N、P、Q任意一个发生变化，即执行赋值语句。
BEGIN
Y<=M+N+P+Q;--相加
END PROCESS;
END ARCHITECTURE ART;--结束