Question

跪求可预置带计数使能异步复位加法计数器的VHDL程序。。

Answer 1

Library ieee;
use ieee.std_logic_1164.all;
entity counter_n is
port(data:in std_logic_vector(7 downto 0);
load,en,clk,rst: std_logic;
q:out std_logic_vector(7 downto 0));
end counter_n;
architecture behave of counter_n is
signal count:std_logic _vectore(7 downto 0);
begin
process(clk,rst)
begin
if rst=’1’ then
count <=(others=>'0')
elsif clk'event and clk='1' then
if load=’1’ then
count<=data;
elsif en='1’ then
count<=count+1;
end if;
end if;
end process;
Q<=count;
end behave;
大笨蛋

Answer 2

来我教你..