Question

jk触发器的VHDL语言描述！

谁给个我！

Answer 1

library ieee;
use ieee.std_logic_1164.all;
entity jk is
port(j,k,clk: in std_logic;
q,nq: buffer std_logic);
end;
architecture behave of jk is
begin
process(j,k,clk) variable q_r,nq_r:std_logic;
begin
if(clk'event and clk='1')then
if(j='0')and(k='1')then
q_r:='0';
nq_r:='1';
elsif (j='1')and(k='0')then
q_r:='1';
nq_r:='0';
elsif(j='1')and(k='1')then
q_r:=not q;
nq_r:=not nq;
end if;
end if;
q<=q_r;
nq<=nq_r;
end process;
end;