Question

quartus ii 13.0 调用modelsim仿真时出错， Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic

十进制计数器，VHDL代码
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY CNT10 IS
PORT(RST,CLK,EN : IN STD_LOGIC;
CQ : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
COUNT : OUT STD_LOGIC);
END CNT10;
ARCHITECTURE BEHAV OF CNT10 IS
BEGIN
PROCESS(RST, CLK, EN)
VARIABLE CQI : STD_LOGIC_VECTOR(3 DOWNTO 0);
BEGIN
IF RST= '1' THEN CQI := (OTHERS => '0');
ELSIF CLK'EVENT AND CLK = '1' THEN
IF EN = '1' THEN
IF CQI < 9 THEN CQI := CQI+1;
ELSE CQI := (OTHERS => '0'); END IF;
END IF;
END IF;
IF CQI = 9 THEN COUNT <= '1';
ELSE COUNT <= '0';
END IF;
CQ <= CQI;
END PROCESS;
END BEHAV;

生成的Test-Bench 如下（上述错误说是要赋初值，下面的Test-Bench应该怎么改呢）
LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY CNT10_vhd_tst IS
END CNT10_vhd_tst;
ARCHITECTURE CNT10_arch OF CNT10_vhd_tst IS
-- constants
-- signals
SIGNAL CLK : STD_LOGIC ;
SIGNAL COUNT : STD_LOGIC ;
SIGNAL CQ : STD_LOGIC_VECTOR(3 DOWNTO 0) ;
SIGNAL EN : STD_LOGIC ;
SIGNAL RST : STD_LOGIC ;
COMPONENT CNT10
PORT (
CLK : IN STD_LOGIC;
COUNT : OUT STD_LOGIC;
CQ : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
EN : IN STD_LOGIC;
RST : IN STD_LOGIC
);
END COMPONENT;
BEGIN
i1 : CNT10
PORT MAP (
-- list connections between master ports and signals
CLK => CLK,
COUNT => COUNT,
CQ => CQ,
EN => EN,
RST => RST
);
init : PROCESS
-- variable declarations
BEGIN
-- code that executes only once
WAIT;
END PROCESS init;
always : PROCESS
-- optional sensitivity list
-- ( )
-- variable declarations
BEGIN
-- code executes for every event on sensitivity list
WAIT;
END PROCESS always;
END CNT10_arch;

Answer 1

你的testbench有问题

没有加激励

你把这段话改成我后面的那段

init : PROCESS                                             
-- variable declarations                                   
BEGIN                                                      
        -- code that executes only once                    
WAIT;                                                     
END PROCESS init;                                         
always : PROCESS                                            
-- optional sensitivity list                                
-- (        )                                               
-- variable declarations                                    
BEGIN                                                       
        -- code executes for every event on sensitivity list
WAIT;                                                      
END PROCESS always;

 

 

下面是添加的clk和激励：

CLK_process :process
   begin
  CLK <= '0';
  wait for 10 ns;
  CLK <= '1';
  wait for 10 ns;
   end process;
 
 stim_proc: process
    begin  
      wait for 20 ns;

      EN <='1';

      RST <= '1'; 
  wait for 10 ns;
  RST <= '0';
      wait;

end process;

我试过可以完美仿真，顺便贴张仿真结果给你吧：）