Question

请帮忙翻译一下（急用）

COMBINING PARALLEL LIFTING AND RETIMING ARCHITECTURE FOR DISCRETE WAVELET TRANSFORM
ABSTRACT
The implementation based on lifting scheme of discrete wavelet transform has great advantages compared with that based on convolution. However, the critical path of the conventional lifting algorithm based implementation is potentially longer than that of convolution-based implementation. In this paper, an improved lifting algorithm for the (6,101 wavelet filters and its VLSI architecture are presented, in which parallelism of arithmetic operations in each lifting step is exploited, and a retiming technique is employed to optimize design. Compared with the other works reported in previous literature, the proposed architecture is a more efficient altemative in reducing critical path and hardware cost.
1.introduction
The discrete wavelet transform (DWT) is widely used in many areas, such as signal analysis and image compression etc. The DWT has been adopted to be an ingredient in many image compression standards, such as JPEG2000 [I], because it can decompose the signals into different subbands with both time and frequency information and facilitate to arrive a high compression ratio. Hardware implementation for the DWT is efficient to meet real-time. Recently, a number of works [2-81 have been reported that focus on reducing complexity and latency of the VLSI architecture for DWT. The implementation based on lifting
scheme of discrete wavelet transform has great advantages compared with that based on convolution [2]. However, the critical path of the conventional
lifting algorithm based implementation (CLABI) [4] is potentially longer than that of convolution-based implementation (CBI) [4]. Despite the delay can be reduced by employing pipeline technique 191, it wIll increase the complexity of hardware implementation. A reschedule technique was employed in [6] to increase working frequency. A flipping structure has
been presented in [SI to reduce efficiently the critical path with lower hardware complexity. In this paper, an improved lifting algorithm for the (6,iO) wavelet filters and its VLSI architecture are presented, in which parallelism of arithmetic operations in each lifting step is exploited, and a retiming technique is employed to optimize design. Compared with the other works reported in previous literature, the proposed architecture is a more efficient altemative in reducing critical path and hardware cost. The rest of the paper is organized as follows. In Section 2, a brief review for lifting scheme of discrete wavelet transform is described, followed by a new lifting scheme for the (6,lO) discrete wavelet filters is presented in Section 3. The proposed architectures for the (6,lO) wavelet filters are illustrated in Section 4. followed by the performance analysis and comparison with other designs. Conclusions for this paper are drawn in Section 5.
2. LIFTING SCHEME OF DWT
Lifting scheme is a new method to construct wavelet bases, which was first introduced by Sweldens in 1990s
[Z]. It was originally developed from the eartier work of Donoho to build the wavelet from interpolating scaling functions and the work of Lounsbery et al., which constructed the wavelet for a polyhedral surface. The main difference with such classical constructions as [2] and [3] is that it entirely relies on the spatial domain. Therefore, it is suitable for constructing wavelets that lack translation and dilation, and thus, the Fourier transform is no longer available.
有追加

Answer 1

结合平行的举和RETIMING建筑学为分离小波变换

实施根据分离小波举的计划变换有巨大好处和那相比根据卷积的摘要。 然而，常规举的算法基于实施的关键路程比那潜在地长基于卷积的实施。 在本文，一种被改进的举的算法为(提出6,101小波过滤器和它的VLSI建筑学，算术运算平行性在每举的步被利用，并且一个retiming的技术被使用优选设计。 比较其他工作在早先文学报告了，提出的建筑学是一更加高效率altemative在减少关键路程和硬件费用。

分离小波变换的1.introduction (DWT)是用途广泛在许多区域，例如信号分析和图像压分离小波变换(DWT)是用途广泛在许多区域，例如信号分析和图像压缩等。 因为它可能分解信号入不同的次能带以时间和频率信息和促进到达高压缩比， DWT在许多图像压缩标准被采取是一种成份，例如JPEG2000 [I]。 硬件实现为DWT是高效率见面实时。 最近，一定数量的工作[2-81在减少VLSI建筑学的复杂和潜在因素报告了那个焦点为DWT。 根据分离小波举的计划
的实施变换有巨大好处比较根据卷积的那[2]。 然而，常规举的算法基于实施
(CLABI) [4的]关键路程比那潜在地长基于卷积的实施(CBI) [4]。 尽管延迟可以被使用管道技术减少191，它将增加硬件实现的复杂。 重新编排技术被使用[6]增加运作的频率。 提出了一个
翻转的结构[高效率地减少关键路程的SI以更低的硬件复杂。 在本文，一种被改进的举的算法为(6， iO)小波过滤器和它的VLSI建筑学被提出，算术运算平行性在每举的步被利用，并且一个retiming的技术被使用优选设计。 比较在早先文学报告的其他工作，提出的建筑学是一更加高效率altemative在减少关键路程和硬件费用。 本文的其余如下被组织。在第2部分，简要的回顾为分离小波举的计划在第3部分变换由一份新的举的计划描述，跟随为(6， lO)分离小波过滤器被提出。 提出的建筑学为(6， lO)小波过滤器在第4部分被说明。 由性能分析和比较跟随与其他设计。 结论为本文在第5部分被总结。
问题补充：2.DWT举的计划举的计划是修建小波基地的一个新的方法，由Sweldens在90年代。
[Z]首先介绍。 它从Donoho eartier工作最初被开发修造小波从等内插结垢作用和Lounsbery工作，修建小波为polyhedral表面。 主要区别与这样古典建筑象[2]和[3]是它整个地依靠空间领域。 所以，它为修建缺乏翻译和扩张的小波是适当的，并且因而，傅立叶变换不再是可利用的。

Answer 2

结合并行的起吊和定时结构的离散小波变换
摘要
实施基于提升计划的离散小波变换有很大的优势相比，与基于卷积。但是，关键路径的传统的基于提升算法的执行是有潜在长于卷积为基础的执行情况。在这方面的文件，提出了一种改进提升算法为（ 6101小波滤波器及其VLSI结构介绍，在这种并行算术运算，在每一个步骤是取消剥削，并定时技术是受聘的优化设计。相比，与其他工程的报道在过去的文献，建议建筑是一个更有效率的altemative在减少关键路径和硬件成本。
1.introduction
离散小波变换（ DWT ）是广泛使用在许多领域，如信号分析和图像压缩等载重吨已通过成为一个成分，在许多图像压缩标准，如JPEG2000的[一] ，因为它可以分解信号分成不同的子带都与时间和频率的信息和方便到达的高压缩比。硬件实现，为载重吨，是有效率，以满足实时时间。最近，一些工程[ 2-81已报告说，重点是减少复杂性和潜伏期的VLSI结构载重吨。实施基于提升
计划离散小波变换有很大的优势相比，与基于卷积[ 2 ] 。但是，关键路径的传统
基于提升算法的执行情况（ clabi ） [ 4 ]是有潜在长于卷积为基础的执行情况（工业联盟） [ 4 ] 。尽管延误可减少雇用管道技术191 ，它会增加复杂的硬件实现。一改技术，受聘于[ 6 ] ，以增加工作频率。一翻开结构
已提交的在[硅，以减少有效的关键路径与较低的硬件复杂度。在这方面的文件，提出了一种改进提升算法为（ 6 ，印务局）小波滤波器及其VLSI结构介绍，在这种并行算术运算，在每一个步骤是取消剥削，并定时技术是受聘的优化设计。相比，与其他工程的报道，在过去的文献，建议建筑是一个更有效率的altemative在减少关键路径和硬件成本。其余的文件，是有组织如下。在第2条中，简要回顾了取消计划的离散小波变换的描述，其次是一种新的提升方案为（ 6 ，卢）离散小波过滤器是在第3 。建议的架构为（ 6 ，卢）小波滤波器，说明在第4节。其次是性能分析和比较，与其他的设计。结论本文得出在第5 。
取消计划载重吨
取消计划是一个新的方法构建小波基地，这是首次推出的sweldens在20世纪90年代
[ z ] 。它本来是发达国家从eartier工作donoho建设小波从插值尺度的职能和工作lounsbery等人，其中兴建小波一个多面体的表面。主要区别与这种古典建筑，作为[ 2 ] [ 3 ]是，它完全依赖于空间域。因此，这是适合建设小波缺乏翻译和扩张，因此，傅立叶变换是不再可用。

Answer 3

This scheme is called the second-generation wavelets. Obviously, it can be used to build first-generation wavelets and leads to a faster, full in-place implementation of the wavelet transform. The basic idea behind the lifting scheme is a relationship among all biorthogonal wavelets that share the same scaling function such that one can construct the desired wavelet from a simple one. Daubechies and Sweldens proved [3] that any wavelet with FIR filters can be factorized into a finite number of alternating lifting and dual lifting steps starting from the Lazy wavelet. This implies that any wavelet can be derived from arbitrary wavelet, including the Lazy wavelet, by a finite number of lifting and dual lifting.
The main feature of the lifting-based DWT scheme is to break up the high-pass and low-pass filters into a sequence of upper and lower triangular matrices and convert the filter implementation into banded matrix
multiplications [ 3 ] . Such a scheme has several advantages, including "in-place'' computation of DWT,
integer-to-integer wavelet (IWT), symmetric forward and inverse transform etc. Therefore, it comes as no surprise that lifting has been chosen in the new still image compression standard JPEG2000 [ 1].

Let h(z) and g(z) denote the low-pass and high-pass analysis filters, h(z) and g(z) the low-pass
and high-pass synthesis filters, respectively, then the corresponding decomposition and reconstruction
poIyphase matrices, denoted as p(z) and p(z) , respectively, are defined as follows:
[图]（略）
where he(z) and ge(z) [ho(z) and go(z)] represent the even parts [odd parts] of the Iowpass and highpass wavelet filters, respectively. It has been shown in [2] and [3] that if the h(z) and g(z) are a pair of complementary filters for each other, then the p(z)is always factorized by lifting
scheme as follows [3]:
[图]（略）
in which K is a constant, ;i(z)and s ; ( z ) are denoted as primary lifting and dual lifting polynomial (or vice versa) respectively, and m represents the total lifting steps required.
3. NEW LIFTING SCHEME
The polyphase matrix of the (6,lO) filter can be decomposed as (3) [SI.
[图]（略）
where a, b, c, d, e, f; K2, K, are the corresponding lifting coefficients and scale normalization coefficients,
respectively, which can be referred to [I]. From (1), the parallel-based lifting scheme for forward transform of (6,lO) filter can be obtained as (4):
[图]（略）
We use x[n] to represent the original input sequence, and x[Zn] (x[2n+ I]) to represent even (odd) indexed samples, the intermediate values computed during lifting are denoted as &"'[n] and L'")[n] (m=Z,2), and the lowand high- frequency coefficients are expressed as the sequence L[n] and H[n], respectively. Hence, from (2), the implementation of forward transform for (6, IO) filter can be written as (3) by using mathematical notations.
[图]（略）
4. PROPOSED ARCHITECTURE
From (3), the flow diagram of lifting-based architecture for the (6,lO) filter can be proposed as shown in Fig.1, in which the critical path is calculated as (4T, + U,). While according to (5), The flow diagram of a VLSI architecture based on the proposed PLS (named as PLSAj for the (6,lO)
DWT is illustrated as shown in Fig.Z(a). It can be calculated that the critical path latency of the proposed
PLSA is (T,,, + 4T,) if only the order of addition operations is optimized. The critical path of the architecture shown in Fig.l(a) can be further reduced by pipelining. The proposed PLSA with 2 stages of pipeline denoted as dot lines is shown in Fig.2(b), in which 4 additional pipeline registers are used and the critical path is reduced from (T', + 4T0) to (T, + ZT,). The proposed PLSA with 5 stages of pipeline is shown in Fig.Z(c), in which 11 additional pipeline registers are used and the critical path is reduced to T,. The total number of registers required can be efficiently reduced if the retiming technique is employed. Equations (5a)-(5d) can be rewritten as (6a)-(6d) if retiming is employed. Following (6), a PLS-based architecture combining retiming and 5 stages of pipeline for the (6,lO) 1-D DWT can be proposed as shown in
Fig.2(d). Compared with the architecture shown in Fig.2(c), the total number of register required is reduced from I5 to 14. Performance comparison for the architectures of the (6,iO) filter is illustrated in Table 1. Comparison results demonstrate the PLS-based architectures gains better performance than the flipping structure in the case of (6,lO) filter chosen, and the later is a special case of PLSA
[图]（略）
[图]（略）
Fig.2 Proposed PLS-based architecture (PLSA) of (6,lO) 1-D DWT. (a) PLSA without pipeline, (b) PLSA with 2 stages of pipeline, (c) PLSA with 5 stages of pipeline, (d) PLSA with combining retiming and 5 stages of pipeline

TABLE 1
PERFORMANCE COMPARISON OF ARCHITECTURES FOR
THE (6,lO) I-D DWT
[图]（略）
5. CONCLUSIONS
A modified lifting algorithm for the (6,lO) wavelet filters, as well as the fast VLSI architectures, have been proposed, in which parallelism of arithmetic operations in each lifting step is exploited, and a retiming technique is employed to optimize design. Compared with the previous lifting-based designs, the new implementations is a more efficient altemative in reducing critical path and hardware cost.
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