Question

VHDL语句谁能帮我 解释一下 (在线等~急）

library ieee;
 use ieee.std_logic_1164.all; STD_LOGIC_1164程序包
 use ieee.std_logic_arith.all; std_logic_arith程序包
entity kzq is
port(reset,set_t,start,test,clk,done:in std_logic;
cook,ld_8888,ld_clk,ld_done:out std_logic);
end entity kzq;
architecture art of kzq is
type state_type is(idie,lamp_test,set_clock,timer,done_msg);
signal nxt_state,curr_state:state_type;
begin
process(clk,reset)
begin
if reset='1'then
curr_state<=idie;
elsif clk'event and clk='1'then
curr_state<=nxt_state;
end if;
end process;
process(clk,curr_state,set_t,test,done)is
begin
nxt_state<=idie;
ld_8888<='0';
ld_done<='0';
ld_clk<='0';
case curr_state is
when lamp_test=>ld_8888<='1';cook<='0';
when set_clock=>ld_clk<='1';cook<='0';
when done_msg=>ld_done<='1';cook<='0';
when idie=>

--ymq.vhd
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity ymq47 is
port(ain4:in std_logic_vector(3 downto 0);
dout7:out std_logic_vector(6 downto 0));
end entity ymq47;
architecture art of ymq47 is
begin
process(ain4)
begin
case ain4 is
when"0000"=>dout7<="0111111";
when"0001"=>dout7<="0000110";
when"0010"=>dout7<="1011011";
when"0011"=>dout7<="1001111";
when"0100"=>dout7<="1100110";
when"0101"=>dout7<="1101101";
when"0110"=>dout7<="1111101";
when"0111"=>dout7<="0000111";
when"1000"=>dout7<="1111111";
when"1001"=>dout7<="1101111";
when"1010"=>dout7<="1011110";
when"1011"=>dout7<="1011100";
when"1100"=>dout7<="1010100";
when"1101"=>dout7<="1111001";
when others=>dout7<="0000000";
end case;
end process;
end architecture art;

--dcnt6.vhd
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity dcnt6 is
port(clk:in std_logic;
load:in std_logic;
ena:in std_logic;
datain:in std_logic_vector(3 downto 0);
cq:out std_logic_vector(3 downto 0);
carry_out:out std_logic);
end entity dcnt6;
architecture art of dcnt6 is
signal cqi:std_logic_vector(3 downto 0);
begin
process(clk,load,ena)
begin
if load='1'then
cqi<=datain;
elsif clk'event and clk='1'then
if ena='1'then
if cqi="0000"then cqi<="0101";
else cqi<=cqi-'1';
end if;
end if;
end if;
end process;
process(clk)
begin
if clk'event and clk='1'then
if cqi="0000" then carry_out<='1';
else carry_out<='0';
end if;
end if;
end process;
cq<=cqi;
end architecture art;
--dcnt10.vhd
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity dcnt10 is
port(clk:in std_logic;
load:in std_logic;
ena:in std_logic;
datain:in std_logic_vector(3 downto 0);
cq:out std_logic_vector(3 downto 0);
carry_out:out std_logic);
end entity dcnt10;
architecture art of dcnt10 is
signal cqi:std_logic_vector(3 downto 0);
begin
process(clk,load,ena)is
begin
if load='1' then
cqi<=datain;
elsif clk'event and clk='1'then
if ena='1'then
if cqi="0000"then cqi<="1001";
else cqi<=cqi-'1';
end if;
end if;
end if;
end process;
process(clk,cqi)
begin
if clk'event and clk='1'then
if cqi="0000"then carry_out<='1';
else carry_out<='0';end if;
end if;
end process;
cq<=cqi;
end architecture art;

Answer 1

弄懂一个VHDL程序的功能的睁举便捷方法是先看逗早誉输入输出信号有哪些，然后从architecture里找出输入输出之间的逻辑关系。
第一个程序kzq不全，没有细看。
第二个程序ymq.vhd是七段译码器的程序，输入山段一个四位的二进制数（0到13），输出的是七段译码管上的信号。楼主可查一下“七段译码管”。
第三个程序dcnt6.vhd是一个减法计时器，计数值为6，即5，4，3，2，1，0，5，4，……这样数。
补充的dcnt10.vhd就是从第三个程序改了一下数，计数值改为10，每次从9倒数到0再回到9倒数。