Question

FPGA，频率计，数码管显示问题！

做频率计，到数码管显示，烧入板中，显示乱码，不知道什么问题，也不知道扫描时钟怎么设置，下面程序的CLK，指的是什么？？求大神解答！
LIBRARY IEEE;
use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all;
entity display is
port(in7,in6,in5,in4,in3,in2,in1,in0:in std_logic_vector(3 downto 0); lout7:out std_logic_vector(7 downto 0); SEL:OUT STD_LOGIC_VECTOR(2 DOWNTO 0); clk:in std_logic
);
end display;
architecture phtao of display is signal s:std_logic_vector(2 downto 0); signal lout4:std_logic_vector(3 downto 0); begin
process (clk) begin
if (clk'event and clk='1')then if (s="111") then
s<="000";
else s<=s+1;
end if;
end if; sel<=s; end process;
process (s) begin case s is when "000"=>lout4<=in6;
when "001"=>lout4<=in5;
when "010"=>lout4<=in4;
when "011"=>lout4<="0000";
when "100"=>lout4<=in3;
when "101"=>lout4<=in2;
when "110"=>lout4<=in1;
when "111"=>lout4<="0000";
when others=>lout4<="XXXX";
end case;
case lout4 is
when "0000"=>lout7<="00111111";
when "0001"=>lout7<="00000110";
when "0010"=>lout7<="01011011";
when "0011"=>lout7<="01001111";
when "0100"=>lout7<="01100110";
when "0101"=>lout7<="01101101";
when "0110"=>lout7<="01111101";
when "0111"=>lout7<="00000111";
when "1000"=>lout7<="01111111";
when "1001"=>lout7<="01100111";
when "1010"=>lout7<="00111111";
when "1111"=>lout7<="01000000";
when others=>lout7<="XXXXXXXX";
end case;
end process;
end phtao;

Answer 1

数码管共阴共阳的编码不一样，还有数码管abcdefg编码的顺序跟引脚分配是否对应。

Answer 2

你是共阴极还是共阳极数码管？估计是这个地方错了