Question

刚刚接触fpga。请大神帮忙解释下面这段Verilog HDL语言的意思！

always @ (posedge link_clk)begin
case(count[2:0])
3'd0:begin
adc_a_mclk <= 1'b0;
adc_a_sclk <= 1'b0;

end
3'd1:begin
adc_a_mclk <= 1'b0;
adc_a_sclk <= 1'b0;

end
3'd2:begin
adc_a_mclk <= 1'b1;
adc_a_sclk <= 1'b0;

a_d_r1 <= data_rx1; // rs data
a_d_r2 <= data_rx2;
end
3'd3:begin
adc_a_mclk <= 1'b1;
adc_a_sclk <= 1'b0;
end

Answer 1

always @ (posedge link_clk)begin
case(count[2:0])
3'd0:begin // cnout 为0 的时候，下面两个寄存器为0
adc_a_mclk <= 1'b0;
adc_a_sclk <= 1'b0;

end
3'd1:begin // cnout 为1的时候，下面两个寄存器为0
adc_a_mclk <= 1'b0;
adc_a_sclk <= 1'b0;

end
3'd2:begin// cnout 为2的时候，adc_a_mclk为1，adc_a_sclk为0 同时更新
// a_d_r1 a_d_r2 寄存器的值
adc_a_mclk <= 1'b1;
adc_a_sclk <= 1'b0;

a_d_r1 <= data_rx1; // rs data
a_d_r2 <= data_rx2;
end
3'd3:begin// cnout 为1的时候，adc_a_mclk为1，adc_a_sclk为0
adc_a_mclk <= 1'b1;
adc_a_sclk <= 1'b0;
end

综上 adc_a_mclk 类似一个4分频时钟，同时在 count为2的时候，锁存了两个寄存器的值
adc_a_sclk 貌似没用到

追问

什么叫四分频时钟啊！！

Answer 2

always @ (posedge link_clk)begin //link_clk上升沿时
case(count[2:0])
3'd0:begin //当count=0时，adc_a_mclk <= 1'b0;adc_a_sclk <= 1'b0;
adc_a_mclk <= 1'b0;
adc_a_sclk <= 1'b0;

end
3'd1:begin //当count=0时，adc_a_mclk <= 1'b0;adc_a_sclk <= 1'b0;
adc_a_mclk <= 1'b0;
adc_a_sclk <= 1'b0;

end
3'd2:begin //当count=0时，adc_a_mclk <= 1'b1;adc_a_sclk <= 1'b0;data_rx1赋值给a_d_r1，data_rx2赋值给a_d_r2
adc_a_mclk <= 1'b1;
adc_a_sclk <= 1'b0;

a_d_r1 <= data_rx1; // rs data
a_d_r2 <= data_rx2;
end
3'd3:begin //当count=0时，adc_a_mclk <= 1'b1;adc_a_sclk <= 1'b0;
adc_a_mclk <= 1'b1;
adc_a_sclk <= 1'b0;
end