Question

FPGA编写的减法计数器！

请高人帮忙编写下一个25的减法计数器，就是从24一直到0截止的，用FPGA编写！！！正确追加200
VHDL的就可以了

Answer 1

要VHDL的还是Verilog的？

entity lcnt is
port(clk:in std_logic;
q:out std_logic);
end lcnt;
architecture art of lcnt is
signal count:std_logic(4 downto 0);
begin
process(clk)
begin
if clk'event and clk='1' then
if count='0' then
count<=24;
else count<=count-1;
end if;
end if
end process;
end art;

望采纳
你说要追加200分的哦

Answer 2

别逗了，最多只能追加50分。
entity lcnt is
port(clk:in std_logic;
q:out std_logic);
end lcnt;
architecture art of lcnt is
signal count:std_logic(4 downto 0);
begin
process(clk)
begin
if clk'event and clk='1' then
if count='0' then
count<=24;
else count<=count-1;
end if;
end if
end process;
end art;