Question

VHDL中仿真的一个问题

内容很简单，就是先给一个地址，和一个数，我们吧这个数存入一个数组，而地址则表示这个数存在这个数组的什么位置，然后再给一个地址，把这个地址对应的树输入出来。
源代码
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity top1 is
Port(
addr:in std_logic_vector(9 downto 0);
CS:in std_logic;
WE:in std_logic;
IO_in:in std_logic_vector(0 to 3);
IO_out:out std_logic_vector(0 to 3)
);
end top1;

architecture Behavioral of top1 is
type memory is array(0 to 1023) of std_logic_vector(0 to 3);
signal add_choose:integer range 0 to 1023;
signal static_ram:memory;
begin
add_choose<=conv_integer(addr);
process(CS,IO_in,WE,addr)
begin
if(CS='0')then
if(WE='0')then
static_ram(add_choose)<=IO_in;

elsif(WE='1')then
IO_out<=static_ram(add_choose);
end if;
end if;
end process;
end Behavioral;
其中CS为片选信号，WE=0代表写，=1代表读。
。。。

然后是仿真代码
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;

-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--USE ieee.numeric_std.ALL;

ENTITY toptest1 IS
END toptest1;

ARCHITECTURE behavior OF toptest1 IS

-- Component Declaration for the Unit Under Test (UUT)

COMPONENT top1
PORT(
addr : IN std_logic_vector(9 downto 0);
CS : IN std_logic;
WE : IN std_logic;
IO_in : IN std_logic_vector(0 to 3);
IO_out : OUT std_logic_vector(0 to 3)
);
END COMPONENT;

--Inputs
signal addr : std_logic_vector(9 downto 0) := (others => '0');
signal CS : std_logic := '0';
signal WE : std_logic := '0';
signal IO_in : std_logic_vector(0 to 3) := (others => '0');

--Outputs
signal IO_out : std_logic_vector(0 to 3);
-- No clocks detected in port list. Replace <clock> below with
-- appropriate port name

BEGIN

-- Instantiate the Unit Under Test (UUT)
uut: top1 PORT MAP (
addr => addr,
CS => CS,
WE => WE,
IO_in => IO_in,
IO_out => IO_out
);

-- Clock process definitions

-- Stimulus process
stim_proc: process
begin
-- hold reset state for 100 ns.
wait for 100 ns;
addr<="0000000001";
CS<='0';
WE<='0';
IO_in<="1010";
wait for 100 ns;
WE<='1';

-- insert stimulus here

wait;

end process;

END;
最后仿真结果，为什么in_out一直是UUUU...求助啊。。。。

Answer 1

我看着好像意思是有一个同步的置位。

一般的reset信号都是异步的。很少用同步的复位。如果你确实是想要同步复位，那不用管这个warn。可能你的原本意思也是异步复位，但是你的代码中写错了。

一般的同步复位就是process的敏感变量中没有reset。