Question

verilog中连续ram写读实验中读取的数据滞后一写入的数据个周期是什么原因？

testbench：`timescale 1 ns/ 1 psmodule ip_ram_tb();parameter SYS_PERIOD = 20;//时钟周期//例化模块输入wire、输出regreg sys_clk_tb;reg sys_rst_n_tb;reg ram_wr_en_tb;reg ram_rd_en_tb;reg [1:0] ram_addr_tb;reg [3:0] ram_wr_data_tb;wire [3:0] ram_rd_data_tb;always #(SYS_PERIOD) sys_clk_tb = ~sys_clk_tb; initial begin sys_clk_tb <= 1'b1; sys_rst_n_tb <= 1'b0; #(SYS_PERIOD) sys_rst_n_tb <= 1'b1; ram_wr_en_tb <= 0; ram_rd_en_tb <= 0;end reg [2:0] ram_rw_cnt; //读写计数器always @(posedge sys_clk_tb or negedge sys_rst_n_tb)begin if(!sys_rst_n_tb) //复位 ram_rw_cnt <= 3'd0; else if(ram_rw_cnt == 3'd7) ram_rw_cnt <= 3'd0; else ram_rw_cnt <= ram_rw_cnt + 3'd1;endalways @(posedge sys_clk_tb or negedge sys_rst_n_tb)begin if(!sys_rst_n_tb)begin ram_wr_en_tb <= 1'b0; ram_rd_en_tb <= 1'b0; end else if(ram_rw_cnt >= 3'd0 && ram_rw_cnt <= 3'd3)begin ram_wr_en_tb <= 1'b1; ram_rd_en_tb <= 1'b0; end else if(ram_rw_cnt >= 3'd4 && ram_rw_cnt <= 3'd7)begin ram_wr_en_tb <= 1'b0; ram_rd_en_tb <= 1'b1; end else begin ram_wr_en_tb <= 1'b0; ram_rd_en_tb <= 1'b0; endendalways @(posedge sys_clk_tb or negedge sys_rst_n_tb)begin if(!sys_rst_n_tb) ram_wr_data_tb <= 4'd0; else if(ram_rw_cnt == 3'd0) ram_wr_data_tb <= 4'd0; else if(ram_rw_cnt > 3'd0 && ram_rw_cnt <= 3'd3) ram_wr_data_tb <= ram_wr_data_tb + 4'd1; else ram_wr_data_tb <= 4'd5;endalways @(posedge sys_clk_tb or negedge sys_rst_n_tb)begin if(!sys_rst_n_tb) ram_addr_tb <= 2'd0;// else if(ram_rw_cnt > 3'd0 && ram_rw_cnt <= 3'd3)// ram_addr_tb <= ram_addr_tb + 2'b1;// else if(ram_rw_cnt > 3'd4 && ram_rw_cnt <= 3'd7)// ram_addr_tb <= ram_addr_tb + 2'b1;// else// ram_addr_tb <= 2'd0; else if(ram_rw_cnt == 3'd0 || ram_rw_cnt == 3'd4) ram_addr_tb <= 2'd0; else ram_addr_tb <= ram_addr_tb + 2'b1;endip_ram u_ip_ram ( .sys_clk(sys_clk_tb), .sys_rst_n(sys_rst_n_tb), .ram_wr_en(ram_wr_en_tb), //写使能 .ram_rd_en(ram_rd_en_tb), //读使能 .ram_addr(ram_addr_tb), //地址2位 .ram_wr_data(ram_wr_data_tb), //写数据 .ram_rd_data(ram_rd_data_tb) //读数据); endmodule

Answer 1

你好，写的话是当前的时钟沿就写到memory里去，读的话是当前时钟沿锁地址，然后再将对应的数据送出来。但是一般送出来都是上一次写入的value。因为memory需要时间来更新内部的数据，而读的时候获得地址以后就将memory当前的数据送出去就结束了。所以你当前写入的数据需要等到下次读才能送来。