Question

为什么modelsim仿真时时间信号输出总是高阻

程序：

module doudong(clk,pb_in,pb_out,count_sel);
input clk;
input pb_in;
output pb_out;
output [1:0] count_sel;
reg [23:0] count_high=0;
reg [23:0] count_low=0;
reg pb_reg=0;
reg [1:0] count_sel_reg=0;
assign pb_out=pb_reg;
assign count_sel=count_sel_reg;

always @(posedge clk)
if(pb_in==1'b0)
count_low<=count_low+1;
else
count_low<=24'h000000;

always @(posedge clk)
if(pb_in==1'b1)
count_high<=count_high+1;
else
count_high<=24'h000000;

always @(posedge clk)
if(count_high==24'h4C4B40)
pb_reg<=1'b1;
else if (count_low==24'h4C4B40)
pb_reg<=1'b0;
else
pb_reg<=pb_reg;

always @(posedge pb_reg)
count_sel_reg<=count_sel_reg+1;
endmodule
是一个防抖动程序，计数器门限值到达24'h4C4B40的时候才会输出（时钟频率100MHz，按钮稳定时间至少50ms）
testbench文件：
module doudong_vlg_tst();

reg eachvec;

reg clk;
reg pb_in;

wire [1:0] count_sel;
wire pb_out;
parameter period=10000;

doudong i1 (
.clk(clk),

.count_sel(count_sel),
.pb_in(pb_in),
.pb_out(pb_out)
);
initial
begin
clk=0;
pb_in=1'b1;
end
always begin
repeat(40) begin
#(period)clk=~clk;
pb_in=~pb_in;
end
end
endmodule
我已经给了clk的初始化，但是仿真结果里什么都没，clk是高阻

Answer 1

我帮你仿了一下  可以啊

要不你加上`timescale 1ns/1ns 试试