Question

FPGA 串口通信 没有收到数据

Answer 1

module Rx_control_module
(
CLK,nRST,
H2L_Sig,
Bps_Clk,
Rx_En_Sig,
Rx_Pin_IN,

Count_Sig,
Rx_Done_Sig,
Rx_Data
);

input CLK,nRST,H2L_Sig,Bps_Clk,Rx_En_Sig,Rx_Pin_IN;
output Count_Sig,Rx_Done_Sig;
output [7:0]Rx_Data;

reg [3:0]i;
reg [7:0]rData;
reg Is_Count;
reg Is_Done;

always@(posedge CLK or negedge nRST)

if(!nRST)
begin
i<=4'd0;
rData<=8'd0;
Is_Count<=1'd0;
Is_Done<=1'd0;
end
else if(Rx_En_Sig)
case(i)
4'd0:
if(H2L_Sig)begin Is_Count<=1'b1;i<=i+1'b1;end

4'd1:
if(Bps_Clk)begin i<=i+1'b1;end

4'd2,4'd3,4'd4,4'd5,4'd6,4'd7,4'd8,4'd9:

if(Bps_Clk)begin rData[i-2]<=Rx_Pin_IN;i<=i+1'b1;end

4'd10,4'd11:
if(Bps_Clk)begin i<=i+1'b1;end

4'd12:
begin i<=i+1'b1;Is_Count<=1'b0;Is_Done<=1'b1;end

4'd13:
begin i<=4'd0;Is_Done<=1'b0;end
endcase

assign Count_Sig=Is_Count;
assign Rx_Done_Sig=Is_Done;
assign Rx_Data=rData;

endmodule

这是我原来写的读，可以用的