Question

请帮忙写一下主从Jk触发器的程序，不是边沿JK触发器。用VHDL语言，行为描述，结构描述、RTL描述都可以

Answer 1

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY m_s_jkff IS

PORT (cp, j, k: IN std_logic; q, q_n: BUFFER std_logic);
END m_s_jkff;
ARCHITECTURE rtl OF m_s_jkff IS

SIGNAL q1, q1_n: std_logic;
BEGIN
q1 <= q1_n NAND ( NOT(cp AND j AND q_n));
q1_n <= q1 NAND ( NOT(cp AND k AND q));
q <= q_n NAND (NOT cp NAND q1);
q_n <= q NAND (NOT cp NAND q1_n);
END rtl;