Question

vhdl语言，根据给出的异步复位功能的模16加法计数器，写一个带同步复位功能的模10的加法计数器。

library ieee;
useieee.std_logic_1164.all;
useieee.std_logic_unsigned.all;

entity cnt16 is
port(clk,clr : instd_logic;
q:buffer std_logic_vector(3 downto 0));
end;

architecture one ofcnt16 is
begin
process(clr,clk)
begin
ifclr=’1’ thenq<=”0000”;
elsifclk’event and clk=’1’ then
q<=q+1;
endif;
endprocess;
end;

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Answer 1

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
entity cnt10 is
port(clk,clr : in std_logic;
cnt: buffer std_logic_vector(3 downto 0)
);
end cnt10;
architecture aa of cnt10 is
begin
process(clr,clk)
begin
wait until clk'event and clk='1'
if (clr ='1'or cant=9) then
cnt<="0000";
else
cnt <= cnt+ 1;
end if;
end process;
end cant;

Answer 2

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
entity cnt10 is
port(
clk,clr : in std_logic;
q : buffer std_logic_vector(3 downto 0)
);
end;
architecture one of cnt10 is
signal count : integer range 0 to 9:=0;
begin
process(clr,clk)
begin
if(clk'event and clk='1')then
if (clr ='1') then
q<="0000";
else
count <= count + 1;
if(count = 9) then
count <= 0;
q <= q+1;
end if;
end if;
end if;
end process;
end;
end;

追问

process（clr，clk）这句有人说clr要去掉，请问需要么？谢谢了

追答

可以去掉。