Question

VHDL编译错误

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
--*********************************************
ENTITY sy3 is
PORT(a,b,d0,d1,d2,d3 :in std_logic; y :OUT std_logic）;

END sy3 ; *********************************************
ARCHITECTURE abc OF sy3 IS

BEGIN
y<=d0 when a='0'and b='0' else
d1 when a='0' and b='1' else
d2 when a='1' and b='0' else
d3 when a='1' and b='1';
end abc;

错误提醒：
Error: Current license file does not support the EPF10K10LC84-4 device
Error: Quartus II Fitter was unsuccessful. 1 error, 1 warning
Info: Allocated 130 megabytes of memory during processing
Error: Processing ended: Sat Apr 25 12:22:14 2009
Error: Elapsed time: 00:00:00
Error: Quartus II Full Compilation was unsuccessful. 1 error, 2 warnings
我不知道错在哪，怎么改，有哪位好心人可以帮帮忙

Answer 1

不知楼主是不是用QUARTUS2破解版的,我用MAXPLUS2可以编绎，估计是你的QURATUS的LICENSE 问题。与语法无关。。

Answer 2

找一个破解文件(网上到处都是),把hostid改为自己的网卡号