Question

用verilog 如何写vga 显示时钟

Answer 1

给你我写过的
reg[10:0] x;
reg[10:0] y;
reg vsync,hsync,de;
always@(posedge lcd_pclk or negedge lcd_reset_n)
if(!lcd_reset_n)
x <= 0;
else
x <= (x>=horizontal_width)? 11'd1:x+11'd1;

always@(posedge lcd_pclk or negedge lcd_reset_n)
if(!lcd_reset_n)
hsync <= 0;
else
hsync <= (x>horizontal_sync);
assign lcd_hsync = hsync;

always@(posedge lcd_pclk or negedge lcd_reset_n)
if(!lcd_reset_n)
y <= 0;
else if(x==horizontal_width)
y <= (y>=vertical_width)? 11'd1:y+11'd1;

always@(posedge lcd_pclk or negedge lcd_reset_n)
if(!lcd_reset_n)
vsync <= 0;
else
vsync <= (y>vertical_sync);
assign lcd_vsync = vsync;

always@(posedge lcd_pclk or negedge lcd_reset_n)
if(!lcd_reset_n)
de <= 0;
else
de <= (y>vertical_sync+vertical_back_porch) & (y<=vertical_sync+vertical_back_porch+vertical_active) &
(x>horizontal_sync+horizontal_back_porch) & (x<=horizontal_sync+horizontal_back_porch+horizontal_active);
assign lcd_de = de;

Answer 2

你是要显示的时序吧，包括行场同步信号那些吧。