Question

一个vhdl顶层程序中出现的问题

程序如下：
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity system is
port (clk,fin,en,d,c,b,a:in std_logic;
n:in std_logic_vector(7 downto 0);
fout:inout std_logic);
end entity system;
architecture art5 of system is
component yxor is
port (x1,x2:in std_logic);
end component yxor;
component id_controller is
port (inc,dec,clk:in std_logic;
out1:out std_logic);
end component id_controller;
component count_k is
port (clk,updn,en,d,c,b,a:in std_logic;
inc,dec:out std_logic);
end component count_k;
component div is
port (clk:in std_logic;
n:in std_logic_vector(7 downto 0);
y:out std_logic);
end component div;
signal s1,s2,s3,s4,s5:std_logic;
begin
u1:yxor port map(fin,fout,s2);
u2:count_k port map(clk,s2,en,d,c,b,a,s3,s4);
u3:id_controller port map(s3,s4,clk,s1);
u4:div port map(s1,n,fout);
end architecture art5;
quartus2编译后出现如下错误:
Error (10589): VHDL Port Map Aspect error at system.vhd(28): too many actuals for block "yxor" with only 2 formals
Info (10499): VHDL information at system.vhd(10): object "yxor" is declared here
其中yxor，id_controller，count_k，div是4个子程序。
我知道问题所在了!yxor少了一个输出。但是我+上输出后，上面部分的程序变化为:
component yxor is
port (x1,x2:in std_logic;
y:out std_logic);
end component yxor;
.......

begin
u1:yxor port map(fin,fout,s2);
u2:count_k port map(clk,s2,en,d,c,b,a,s3,s4);
u3:id_controller port map(s3,s4,clk,s1);
u4:div port map(s1,n,fout);
end architecture art5;
错误如下：
Error: Node instance "u1" instantiates undefined entity "yxor"
Error: Quartus II Analysis & Synthesis was unsuccessful. 1 error, 0 warnings
Info: Allocated 154 megabytes of memory during processing
Error: Processing ended: Wed Jun 03 12:06:46 2009
Error: Elapsed time: 00:00:03
Error: Quartus II Full Compilation was unsuccessful. 1 error, 0 warnings
请问是什么原因？

Answer 1

有事这个问题

把底层文件拷贝到工程目录下

在工程设置中 ADD 也就是 添加底层文件

再次进行编译即可

Answer 2

你使用了元件调用功能,你要确认库里有没有该元件.
yxor这个元件如果没有,你就在程序里定义一下..
问题就解决了..