Question

使用vhdl语言编一个共阴极数码管译码电路，要求译码0~9，其余不显示。

急急

Answer 1

library ieee;
use ieee,std_logic_164.all;
entity del7 is
port(a:in std_logic_vector(3 downto 0);
led7:out std_logic_vector(6 downto 0));
end entity;
architecture one of del7 is
begin
process(a)
begin
case a is
when"0000"=>led7<="0111111";
when"0001"=>led7<="0000110";
when"0010"=>led7<="0111111";
when"0011"=>led7<="0111111";
when"0100"=>led7<="0111111";
when"0101"=>led7<="0111111";
when"0110"=>led7<="0111111";
when"0111"=>led7<="0111111";
when"1000"=>led7<="0111111";
when"1001"=>led7<="0111111";
when others=>null;
end case;
end process;
end;
把when后面的译码输出改为对应就行了，这里就不给你改了