Question

关于verilog里的module调用问题，例如下，怎么写才能使下例成功运行，谢谢先

`timescale 1ns/100ps
module testbench ();

reg a;
//reg b;
wire c;

trrry DUT (
.a(a),
//.b(b),
.c(c)
);

initial begin
a = 1;

end

endmodule

module trrry(a, c);
input a,
reg b,
output c,

ad ad(.a, .b);

bc bc(.b, .c);

endmodule

module ad(a, b);
input wire a;
output reg b;

always @ (*)
b = a;

endmodule

module bc(b, c);
input wire b;
output reg c;

always @ (*)
c = b;

endmodule

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Answer 1

`timescale 1ns/100ps
module testbench ();

reg a;
//reg b;
wire c;

trrry DUT (
.a(a),
//.b(b),
.c(c)
);

initial begin
a = 1;

end

endmodule

module trrry(a, c);
input a;
wire b;
output c;

ad ad(.a, .b);

bc bc(.b, .c);

endmodule

module ad(a, b);
input wire a;
output b;

always @ (*)
b = a;

endmodule

module bc(b, c);
input wire b;
output c;

always @ (*)
c = b;

endmodule

我改了一些，你试试