Question

这个VHDL语言哪里出错啦？

odule T3_1792_2 (codeout,indec);
input[3:0] indec;
output[6:0] codeout;
reg[6:0] codeout;
always@ (indec)
begin
case(indec)
4'd0:codeout=7'b1111110;
4'd1:codeout=7'b0110000;
4'd2:codeout=7'b1101101;
4'd3:codeout=7'b1111001;
4'd4:codeout=7'b0110011;
4'd5:codeout=7'b1011011;
4'd6:codeout=7'b1011111;
4'd7:codeout=7'b1110000;
4'd8:codeout=7'b1111111;
4'd9:codeout=7'b1111011;
default: codeout=7'bx;
endcase

end
endmodule

Error (10500): VHDL syntax error at T3_1792_2.vhd(1) near text "module"; expecting "entity", or "architecture", or "use", or "library", or "package", or "configuration"
Error (10500): VHDL syntax error at T3_1792_2.vhd(5) near text @

Answer 1

你写的是Verilog HDL代码，但却是VHDL源文件的文件后缀（.vhd）。你将文件后缀改成.v之后再编译试试看。