Question

verilog语言问题

我知道哪里错了，但不知道咋改，希望大侠帮下忙哈

module ws(e,cp0,cp1,timer0,timer1,timer2,timer3);
input cp0,e,cp1;
wire cp0,cp1;
output[3:0] timer3,timer2,timer1,timer0;
reg [3:0] timer3,timer2,timer1,timer0;

always@(posedge cp0)
begin

if(~e)
{timer3,timer2,timer1,timer0}<=16'h5959;
else if(timer3==4'h0&&timer2==4'h0&&timer1==4'h0&&timer0==4'h0)
begin {timer3,timer2,timer1,timer0}<={timer3,timer2,timer1,timer0};end
else if(timer2==4'h0&&timer1==4'h0&&timer0==4'h0)
begin timer3<=timer3-1'b1;timer2<=4'h9;timer1<=4'h5;timer0<=4'h9;end
else if (timer1==4'h0&&timer0==4'h0)
begin timer3<=timer3;timer2<=timer2-1'b1;timer1<=4'h5;timer0<=4'h9;end
else if (timer0==4'h0)
begin timer3<=timer3;timer2<=timer2;timer1<=timer1-1'b1;timer0<=4'h9;end
else begin timer3<=timer3;timer2<=timer2;timer1<=timer1;timer0<=timer0-1'b1;end
end

always@(posedge cp1)
begin

if(~e)
{timer3,timer2,timer1,timer0}<=16'h5959;
if(timer3==4'h0&&timer2==4'h0&&timer1==4'h0&&timer0==4'h0)
begin {timer3,timer2,timer1,timer0}<={timer3,timer2,timer1,timer0};end
else if(timer2==4'h0&&timer1==4'h0)
begin timer3<=timer3-1'b1;timer2<=4'h9;timer1<=4'h5;timer0<=timer0;end
else if (timer1==4'h0)
begin timer3<=timer3;timer2<=timer2-1'b1;timer1<=4'h5;timer0<=timer0;end

else begin timer3<=timer3;timer2<=timer2;timer1<=timer1-1'b1;timer0<=timer0;end
end

endmodule
希望大侠帮忙改下哈，积分全送上

Answer 1

你这是非常典型的新手错误，在ISE下的错误说明为：Multi-source in Unit <ws> on signal <timer1<3>>; this signal is connected to multiple drivers.就是说变量被连在多个驱动上。
原因在于你定义的reg型变量NO以及time1和time2都在两个always块中进行了赋值，要知道reg型变量一般只能在一个always块内使用，在其它块中最多也只能读取数值或者进行比较判断，不能再进行赋值，否则就会出现这个问题。time1的4位，加上time2的四位，再加上NO，就是那九个错误了

Answer 2

else if(timer3==4'h0&&timer2==4'h0&&timer1==4'h0&&timer0==4'h0)
begin
{timer3,timer2,timer1,timer0}<={timer3,timer2,timer1,timer0};
end
也许是我太笨，我完全看不出你写“当a,b,c,d都为0，就把a,b,c,d的值赋给a,b,c,d”这样的句子的作用是什么。
——Medied.Lee

Answer 3

大号被封的路过……
问题已经看出来了，你这个问题很有代表性，很多新手都会犯
等我明天解了封再告诉你答案……
居然知道帐号也能被封，没天理了！！！