verilog控制亮灯的问题~急求解
我现在刚开始学VERILOG,由于时间紧迫,哪位可以帮我一下?我用的是EPM570T100C5N的片,晶振是50MHZ.要编写一个用键控制灯的,按一下按键,灯闪烁三次,每...
我现在刚开始学VERILOG,由于时间紧迫,哪位可以帮我一下?我用的是EPM570T100C5N的片,晶振是50MHZ.要编写一个用键控制灯的,按一下按键,灯闪烁三次,每次0.5S~万分感谢~
峥峥好 可不可以给我写个verilog的程序呢 这样说 有点抽象 最好有注释哈 其他朋友帮帮忙也!!! 展开
峥峥好 可不可以给我写个verilog的程序呢 这样说 有点抽象 最好有注释哈 其他朋友帮帮忙也!!! 展开
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module led_blinking(led,sw,clk,rst_n);
output led;
input sw;
input clk,rst_n; //10MHz
reg[19:0] cnt; // 按键消抖计时器
always@(posedge clk or negedge rst_n)
if(!rst_n) cnt<=20'd0;
else cnt<=cnt+1'b1;
reg[22:0] cnt1; //计时0.5s计数器,根据时 //钟频率更改位数
always@(posedge clk or negedge rst_n)
if(!rst_n) cnt1<=23'd0;
else cnt1<=cnt1+1'b1;
reg SW_R;
always@(posedge clk or negedge rst_n)
if(!rst_n) SW_R<=1'b1;
else if(cnt==20'hfffff)
SW_R<=sw;
reg SW_R_R;
always@(posedge clk or negedge rst_n)
if(!rst_n) SW_R_R<=1'b1;
else SW_R_R<=SW_R;
wire LED_CTRL=SW_R_R&(~SW_R); //检测按键是否按下
reg [6:0] state,next_state; //状态机
parameter S_Wait=7'b0000001,
S_0=7'b0000010,
S_1=7'b0000100,
S_2=7'b0001000,
S_3=7'b0010000,
S_4=7'b0100000,
S_5=7'b1000000;
always@(posedge clk or negedge rst_n)
if(!rst_n) state<=S_Wait;
else state<=next_state;
always@(state or LED_CTRL or cnt1)
begin next_state<=S_Wait;
case(state)
S_Wait: if(LED_CTRL) next_state<=S_0; else
next_state<=S_Wait;
S_0: if(cnt1==23'h7ffff) next_state<=S_1; else
next_state<=S_0;
S_1: if(cnt1==23'h7ffff) next_state<=S_2; else
next_state<=S_1;
S_2: if(cnt1==23'h7ffff) next_state<=S_3; else
next_state<=S_2;
S_3: if(cnt1==23'h7ffff) next_state<=S_4; else
next_state<=S_3;
S_4: if(cnt1==23'h7ffff) next_state<=S_5; else
next_state<=S_4;
S_5: if(cnt1==23'h7ffff) next_state<=S_Wait; else
next_state<=S_5;
endcase
end
reg led_r;
always@(posedge clk or negedge rst_n) //闪烁3次
if(!rst_n) led_r<=1'b1; else
case(next_state)
S_Wait: led_r=1'b1;
S_0: led_r<=1'b0;
S_1: led_r<=1'b1;
S_2: led_r<=1'b0;
S_3: led_r<=1'b1;
S_4: led_r<=1'b0;
S_5: led_r<=1'b1;
endcase
assign led=led_r;
endmodule
//我也是新手,程序有不足之处,共同学习
output led;
input sw;
input clk,rst_n; //10MHz
reg[19:0] cnt; // 按键消抖计时器
always@(posedge clk or negedge rst_n)
if(!rst_n) cnt<=20'd0;
else cnt<=cnt+1'b1;
reg[22:0] cnt1; //计时0.5s计数器,根据时 //钟频率更改位数
always@(posedge clk or negedge rst_n)
if(!rst_n) cnt1<=23'd0;
else cnt1<=cnt1+1'b1;
reg SW_R;
always@(posedge clk or negedge rst_n)
if(!rst_n) SW_R<=1'b1;
else if(cnt==20'hfffff)
SW_R<=sw;
reg SW_R_R;
always@(posedge clk or negedge rst_n)
if(!rst_n) SW_R_R<=1'b1;
else SW_R_R<=SW_R;
wire LED_CTRL=SW_R_R&(~SW_R); //检测按键是否按下
reg [6:0] state,next_state; //状态机
parameter S_Wait=7'b0000001,
S_0=7'b0000010,
S_1=7'b0000100,
S_2=7'b0001000,
S_3=7'b0010000,
S_4=7'b0100000,
S_5=7'b1000000;
always@(posedge clk or negedge rst_n)
if(!rst_n) state<=S_Wait;
else state<=next_state;
always@(state or LED_CTRL or cnt1)
begin next_state<=S_Wait;
case(state)
S_Wait: if(LED_CTRL) next_state<=S_0; else
next_state<=S_Wait;
S_0: if(cnt1==23'h7ffff) next_state<=S_1; else
next_state<=S_0;
S_1: if(cnt1==23'h7ffff) next_state<=S_2; else
next_state<=S_1;
S_2: if(cnt1==23'h7ffff) next_state<=S_3; else
next_state<=S_2;
S_3: if(cnt1==23'h7ffff) next_state<=S_4; else
next_state<=S_3;
S_4: if(cnt1==23'h7ffff) next_state<=S_5; else
next_state<=S_4;
S_5: if(cnt1==23'h7ffff) next_state<=S_Wait; else
next_state<=S_5;
endcase
end
reg led_r;
always@(posedge clk or negedge rst_n) //闪烁3次
if(!rst_n) led_r<=1'b1; else
case(next_state)
S_Wait: led_r=1'b1;
S_0: led_r<=1'b0;
S_1: led_r<=1'b1;
S_2: led_r<=1'b0;
S_3: led_r<=1'b1;
S_4: led_r<=1'b0;
S_5: led_r<=1'b1;
endcase
assign led=led_r;
endmodule
//我也是新手,程序有不足之处,共同学习
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