已知m序列生成多项式为y=1+x^2+x^3+x^4+x^8求vhdl代码
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library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity PRSG is
port (reset,clk:in std_logic;
sel:in std_logic_vector(1 downto 0);
dout:out std_logic_vector(7 downto 0));
end PRSG;
architecture behavioral of PRSG is
signal ddout:std_logic_vector(7 downto 0);
signal temp:std_logic;
begin
process(sel)
begin
if reset='1' then
ddout
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity PRSG is
port (reset,clk:in std_logic;
sel:in std_logic_vector(1 downto 0);
dout:out std_logic_vector(7 downto 0));
end PRSG;
architecture behavioral of PRSG is
signal ddout:std_logic_vector(7 downto 0);
signal temp:std_logic;
begin
process(sel)
begin
if reset='1' then
ddout
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