Question

如何用VHDL设计七段数码显示器的十六进制译码器，要求该译码器有三态输出

Answer 1

用case语句就可以，当然也可以由with select，when。。。等语句。输出和数码管的接法有关，下面这个是我用case语句写的，是共阴的接法，共阳的话把q按位取反就是。我综合通过了。
library ieee;
use ieee.std_logic_1164.all;

entity smg_16 is
port( a:in std_logic_vector(3 downto 0);
q:out std_logic_vector(6 downto 0)
);
end smg_16;
architecture bhv of smg_16 is
begin
process(a)
begin
case a is
when "0000"=> q<="0111111";
when "0001"=> q<="0000110";
when "0010"=> q<="1011011";
when "0011"=> q<="1001111";
when "0100"=> q<="1100110";
when "0101"=> q<="1101101";
when "0110"=> q<="1111101";
when "0111"=> q<="0100111";
when "1000"=> q<="1111111";
when "1001"=> q<="1101111";
when "1010"=> q<="1110111";
when "1011"=> q<="1111100";
when "1100"=> q<="0111001";
when "1101"=> q<="1011110";
when "1110"=> q<="1111001";
when others=> q<="1110001";
end case;
end process;
end bhv;