Question

为什么我的VERILOG语言编译后程序不执行任何逻辑

代码如下
module spiserve(ad_in,ready,ad_out,sclk,ad_sclk);
input ready,ad_in,sclk,ad_sclk;
output ad_out;
reg reg2,reg3,ad_out,reg1;
reg en1,en2;
reg[4:0] counter,counter2;
reg[23:0] buff1,buff2;
initial reg1=1'b0;
initial reg2=1'b1;
initial reg3=1'b1;
initial counter=0;
initial counter2=0;
always@(negedge ad_sclk or posedge ready)
if(ready==1)
begin reg1=1'b1;
end
else if(reg1&®3&&en1&&en2)
begin
if(counter<=23)
begin buff1[0]<=ad_in;
buff1<=buff1<<1;
counter=counter+1;
end
else
begin
counter=5'b0;
reg1=0;
reg2=1;
reg3=0;
end
end
else if(reg1&®2&&en1&&en2)
begin
if(counter<=23)
begin buff2[0]<=ad_in;
buff2<=buff2<<1;
counter=counter+1;
reg2<=0;
end
else
begin
counter=5'b0;
reg1=0;
reg3=1;
reg2=0;
end
end
else if(reg1&&en1)
begin if(counter<=23)
begin buff1[0]<=ad_in;
buff1<=buff1<<1;
counter=counter+1;
end
else
begin
counter=5'b0;
reg1=0;
reg2=0;
reg3=1;
end
end
else if(reg1&&en2)
begin if(counter<=23)
begin buff1[0]<=ad_in;
buff1<=buff1<<1;
counter=counter+1;
end
else
begin
counter=5'b0;
reg1=0;
reg2=1;
reg3=0;
end
end
// 读AD
always@(posedge sclk )
if(reg2)
begin if(counter2<=23)
begin ad_out=buff1[counter];
en1=0;
en2=1;
counter2<=counter2+1;
end
else
begin counter2=0;
en1=1;
en2=1;
end
end
else begin
if(counter2<=23)
begin ad_out=buff2[counter];
en1=1;
en2=2;
counter2<=counter2+1;
end
else
begin counter2=0;
en1=1;
en2=1;
end
end
endmodule
编译没有任何error 但是有很多warning：

Warning: Reduced register "b2[0]" with stuck data_in port to stuck value GND
Warning: Reduced register "b2[1]" with stuck data_in port to stuck value GND
Warning: Reduced register "b2[2]" with stuck data_in port to stuck value GND..
等等。。。定义的寄存器 每一位都有这个WARNING
。

Answer 1

1. else if(reg1&®2&&en1&&en2), ®是啥运算符?

2. Warning: Reduced register "b2[0]" with stuck data_in port to stuck value GND
   意思是说经综合[编译]完后发现b2[0]相当于一直接GND. 也就是你逻辑错了. Quartus里要将Warning和Error一样看待。Error主要是语法错误，Warning提醒你可能的逻辑错误。

3. 可以用RTL Viewer看综合成的电路是不是你想要的电路。如果是，就可以着手仿真验证了。