Question

xilinx ISE 13.3test bench仿真输出没有波形

test bench测试源码如下
ENTITY test IS
END test;

ARCHITECTURE behavior OF test IS

-- Component Declaration for the Unit Under Test (UUT)

COMPONENT main
PORT(
clk : IN std_logic;
key_in : IN std_logic_vector(5 downto 0);
key_out : OUT std_logic_vector(3 downto 0);
light : OUT std_logic_vector(7 downto 0);
cpld_en : OUT std_logic_vector(1 downto 0);
test_out : OUT std_logic_vector(1 downto 0);
led_en : OUT std_logic_vector(1 downto 0)
);
END COMPONENT;

--Inputs
signal clk : std_logic := '0';
signal key_in : std_logic_vector(5 downto 0) := (others => '0');

--Outputs
signal key_out : std_logic_vector(3 downto 0);
signal light : std_logic_vector(7 downto 0);
signal cpld_en : std_logic_vector(1 downto 0);
signal test_out : std_logic_vector(1 downto 0);
signal led_en : std_logic_vector(1 downto 0);

-- Clock period definitions
constant clk_period : time := 10 ns;

BEGIN

-- Instantiate the Unit Under Test (UUT)
uut: main PORT MAP (
clk => clk,
key_in => key_in,
key_out => key_out,
light => light,
cpld_en => cpld_en,
test_out => test_out,
led_en => led_en
);

-- Clock process definitions
clk_process :process
begin
clk <= '0';
wait for clk_period/2;
clk <= '1';
wait for clk_period/2;
end process;

-- Stimulus process
stim_proc: process
begin
-- hold reset state for 100 ns.
key_in <= "111110";
wait for 100 ns;
key_in <= "011111";
wait for 100 ns;
key_in <= "101111";
wait for 100 ns;
key_in <= "110111";
wait for 100 ns;

-- insert stimulus here

wait;
end process;

END;

Answer 1

你把波形窗口缩的紧一些！

追问

波形窗口缩小可以看到输入的波形这我知道，但是输出波形的颜色都不对，再怎么缩小也不会出来波形啊

Answer 2

变量没有赋初值