Question

vhdl 数组 变量

请问在vhdl中使用数组时，数组能不能被定义成shared variable类型，还是只能被定义成signal。谢谢。
例如：type dist1 is array (3 downto 0) of std_logic_vector(3 downto 0);
signal dist:dist1;--可不可以写成shared variable dist:dist1;

Answer 1

shared variable没问题 用vhdl描述双端口ram就需要用到

比如：
architecture syn of rams_16 is
type RAMtype is array (0 to 255) of std_logic_vector(15 downto 0);
shared variable RAM : RAMtype;
begin
process (CLKA)
begin
if CLKA'event and CLKA = '1' then
if ENA = '1' then
if WEA = '1' then
RAM(conv_integer(ADDRA)) := DIA;
end if;
DOA <= RAM(conv_integer(ADDRA));
end if;
end if;
end process;

process (CLKB)
begin
if CLKB'event and CLKB = '1' then
if ENB = '1' then
if WEB = '1' then
RAM(conv_integer(ADDRB)) := DIB;
end if;
DOB <= RAM(conv_integer(ADDRB));
end if;
end if;
end process;
end syn;

Answer 2

不行，variable只能写在进程中