Question

verilog仿真时钟信号产生问题

本人刚接触verilog 编程，正在摸索着编写一个计数器。需要两路输入信号，一个是时钟clk和重置信号rst，这两个信号都是方波，但是频率不同分别为1MHz和1KHz，在编写测试文件时该如何编写正确的代码呢？小白求指教。我试着写了个但是是有错的。
`timescale 1ns/1ns
module testsamleratecounter;
reg rst,clk_in,counter,counter1,counter2,rst_tmp;
always
begin
#500 clk_in = ~clk_in;
end
always
begin
always
begin
#50000 rst = ~rst;
end
initial
begin
clk_in = 0;
rst = 0;
counter = 8'd0;
counter1 = 8'd0;
counter2 = 8'd0;
rst_tmp = 0;
end
endmodule

Answer 1

你需要用到forever语句：
initial
begin
clk=1'b0;
……
forever #1000 clk = ~clk;
……
end

追问

请问可以这样用产生两路信号么？
initial
begin
clk=1'b0;
rst=1'b0；
forever #500 clk = ~clk;
forever #50000 rst = ~rst;
end

Answer 2

`timescale 1ns/1ns
module testsamleratecounter;
reg rst,clk_in,counter,counter1,counter2,rst_tmp;
always
begin
#500 clk_in = ~clk_in;
end
// always
// begin 这两句写重复了
always
begin
#50000 rst = ~rst;
end
initial
begin
clk_in = 0;
rst = 0;
counter = 8'd0;
counter1 = 8'd0;
counter2 = 8'd0;
rst_tmp = 0;
end
endmodule