Question

verilog程序出现这种错误

代码
module zidongjiashi(clk,clk_jinji,cin,lef,str,div,exc,cor,led1,led2,led3);
input clk,clk_jinji,cin;
output str;
output div;
output exc;
output cor;
output lef;
output led1;
output led2;
output led3;
reg [6:0] state;
reg lef,str,div,exc,cor,led1,led2,led3;
//状态编码
parameter idle= 7'b0000000,
s0= 7'b0000001,
s1= 7'b0000010,
s2= 7'b0000100,
s3= 7'b0001000,
s4= 7'b0010000,
s5= 7'b0100000,
s6= 7'b1000000;
//状态转移
always @ (posedge clk )
begin
case(state)
idle:
if(cin==1'b0) begin state<=s1;end
else begin state<=idle; end
s1:
if(cin==1'b0) begin state<=s2;str<=1'b1;end
else begin state<=idle;str<=1'b0; end
s2:
if(cin==1'b1) begin state<=s3; div<=1'b1;end
else begin state<=idle;div<=1'b0; end
s3:
if(cin==1'b1) begin state<=s4;end
else begin state<=idle; end
s4:
if(cin==1'b1) begin state<=s5;exc<=1'b1;end
else begin state<=idle;div<=1'b1;end
s5:
if(cin==1'b1) begin state<=s6;cor=1'b1;end
else begin state<=idle;div<=1'b1; end
s6:
if(cin==1'b1) begin state<=s5;str<=1'b0; end
else begin state<=s2;div<=1'b1;end
default: begin state<=idle; end
endcase
begin
if(clk_jinji==1'b1) begin str<=1'b0;end
else begin div<=1'b1;end
begin
if(cor==1'b1) if(lef==1'b1)begin led1<=1'b1;end
else begin led2<=1'b1;end
else begin str<=1'b0;end
begin
if(clk_jinji==1'b1)begin led3<=1'b1; str<=1'b0;end
else begin led3<=1'b0; div<=1'b1;end
end
begin
if(div==1'b0)begin str<=1'b0;end
else str<=1'b1;end
endmodule;
错误是Error (10170): Verilog HDL syntax error at /Verilog1.v(63) near text "endmodule"; expecting ";", or "@", or "end", or an identifier ("endmodule" is a reserved keyword ), or a system task, or "{", or a sequential statement

Answer 1

endmodule后面的分号去掉 。
格式风格不太好，把每个begin和每个end对应上，这样方便找问题。
你这个问题就是在语法和标点，完全是代码习惯问题。

Answer 2

endmodule;后面的分号去掉

追问

也不对

Answer 3

倒数第二行的else后面差一个begin

追问

改过以后还是不对

追答

你前面的case语句语法是对的，endcase下面的部分显得比较混论，好多begin没有跟end配对，你还是先弄清楚你要实现的功能，把逻辑理清楚了再写。