Question

求教！延时输出的Verilog代码错在哪里，如何解决？

module delay_release
(
input rst_n,
input clk,
input HV_crtl_switch_2,
input HV_interlock,
output delay_release
);

reg delay_reg;
reg [27:0] count_reg;
reg out_reg;

always@(posedge clk or negedge rst_n)
begin
if(!rst_n)
delay_reg<=1'b0;
count_reg<=28'b0;
out_reg<=1'b0;
else
delay_reg<=HV_crtl_switch_2 & HV_interlock;
end

always@(posedge clk or negedge rst_n)
begin
if(delay_reg==1'b1)
count_reg<=count_reg+1'b1;
if(count_reg==28'd199_999_999)
out_reg<=delay_reg;
else
count_reg<=1'b0;
end

assign delay_release=out_reg;

endmodule

报错：Error (10170): Verilog HDL syntax error at delay_release.v(20) near text "else"; expecting "@", or "end", or an identifier ("else" is a reserved keyword ), or a system task, or "{", or a sequential statement

Answer 1

if,else 内部有多条赋值语句，需要用begin end。